Communication system with low power, DC-balanced serial link

• US 20060165185A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Dally, William J., Poulton, John W.
• Granted Patent: US 7,199,728 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Claims

1. A data communication system, comprising:

a transmission line;

a first integrated circuit coupled to the transmission line and including a transmitter, the transmitter comprising

an encoder, having a data input, that encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced; and

a driver, coupled to the encoder, that drives the sequence of codewords within a corresponding sequence of symbol cells on the transmission line; and

a second integrated circuit coupled to the transmission line and including a receiver, the receiver comprising

an input to receive the sequence of codewords.

2. The system of claim 1, wherein the second integrated circuit includes:

an integrating circuit, coupled to the input, which integrates codewords in the received sequence of codewords to produce output representing the sequence of codewords, including integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, wherein there is one codeword per symbol cell; and

a sense circuit coupled to the integrating circuit, to produce an output data stream.

3. The system of claim 1, wherein the driver drives the sequence of codewords with power of less than 100 picoJoules per bit.

4. The system of claim 1, wherein the encoder comprises a Manchester encoder.

5. The system of claim 1, wherein the set of codewords consists of two members.

6. The system of claim 1, wherein the set of codewords comprises more than two members.

7. The system of claim 1, wherein the set of codewords comprises a first subset of orthogonal code words and a second subset of code words that are complements of the orthogonal code words in the first subset.

8. The system of claim 1, wherein the driver drives the sequence of codewords with less than 50 millivolts swing.

9. The system of claim 1, wherein codewords in the set of codewords include respectively, a binary code word and one of a plurality of voltage swing amplitudes, whereby a particular binary code word with a first voltage swing amplitude represents a first data value, and the particular binary code word with a second voltage swing amplitude represents a second data value.

10. The system of claim 1, wherein the driver drives the sequence of codewords at a data rate sufficient to transmit more than 1 gigabit per second of the input data stream.

11. The system of claim 1, including a multiplexer converting the input data stream from parallel to serial.

12. The system of claim 1, including a multiplexer converting the input data stream from parallel to serial, and using a combined circuit for the multiplexer, encoder and driver.

13. The system of claim 1, including a multiplexer converting the input data stream from parallel to serial, and using a combined circuit for the multiplexer, encoder and driver, and wherein the combined circuit is a push-pull circuit.

14. The system of claim 1, including a multiplexer converting the input data stream from parallel to serial, and using a combined circuit for the multiplexer, encoder and driver, and wherein the combined circuit is a differential circuit.

15. The system of claim 1, wherein the encoder comprises exclusive-OR logic.

16. The system of claim 1, including an integrating circuit coupled to the input on the second integrated circuit, the integrating circuit comprising a combined differential amplifier and exclusive OR circuit.

17. The system of claim 1, including an integrating circuit coupled to the input on the second integrated circuit, the integrating circuit comprising first and second integrating amplifiers, and logic for time-multiplexing the first and second integrating amplifiers.

18. The system of claim 1, including a clock recovery circuit on the second integrated circuit coupled to the input.

19. The system of claim 1, wherein the input on the second integrated circuit includes a component to AC couple the transmission line to the second integrated circuit.

20. The system of claim 1, wherein the transmission line comprises a differential pair of conductors.

21. The system of claim 1, wherein the transmission line comprises a single printed circuit board conductor or a differential pair of printed circuit board conductors.

22. The system of claim 1, wherein the transmission line comprises a twisted pair cable.

23. The system of claim 1, wherein the transmission line comprises a single-ended transmission line.

24. The system of claim 1, wherein the driver drives the sequence of codewords at a data rate using a clock having a frequency that is half of the data rate.

25. The system of claim 1, including a differentiating circuit arranged to couple the driver to the transmission line.

26. A data communication system, comprising:

a transmission line;

a first integrated circuit coupled to the transmission line and including means for encoding and driving a sequence of codewords on the transmission line, wherein codewords in the sequence are members of a set of codewords representing data in an input data stream, and the members of the set are substantially DC balanced; and

a second integrated circuit coupled to the transmission line and including means for receiving and decoding the sequence of codewords from the transmission line.