Semiconductor substrate having reference semiconductor chip and method of assembling semiconductor chip using the same

• US 20060166383A1
• Filed: 01/20/2006
• Published: 07/27/2006
• Est. Priority Date: 01/22/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-moon, Kim, Jung-hye, Kim, Young-bu
• Granted Patent: US 7,618,832 B2
• Time in Patent Office: Days
• US Class Current: 438/15
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

Claims

1. A method of assembling semiconductor chips, comprising:

providing a semiconductor substrate having a plurality of semiconductor chips;

making an identification mark on a reference semiconductor chip among the semiconductor chips; and

aligning the semiconductor substrate referring to the reference semiconductor chip and performing an electrical die sorting test on the semiconductor chips.

2. The method of claim 1, wherein making the identification mark comprises illuminating a laser on the reference semiconductor chip.

3. The method of claim 2, wherein illuminating the laser comprises adjusting the focus size of the laser according to the area of the reference semiconductor chip.

4. The method of claim 2, wherein illuminating the laser comprises transforming a surface of the reference semiconductor chip.

5. The method of claim 1, wherein making the identification mark comprises making a laser mark for identification on the reference semiconductor chip.

6. The method of claim 1, wherein performing the electrical die sorting test comprises storing the test results together with coordinates of the semiconductor chips referring to the reference semiconductor chip.

7. The method of claim 1, further comprising physically separating the semiconductor chips using the test results after performing the electrical die sorting test.

8. The method of claim 7, wherein separating the semiconductor chips comprises sorting the semiconductor substrate referring to the reference semiconductor chip.

9. The method of claim 7, further comprising making ink marks on the semiconductor chips using the test results before separating the semiconductor chips.

10. The method of claim 9, wherein making the ink mark is performed using the coordinates stored at the electrical die sorting test.

11. The method of claim 1, wherein the reference semiconductor chip on the semiconductor substrate is a first semiconductor chip on which the electric die sorting test is performed.

12. A method of assembling a plurality of semiconductor chips by sorting and separating the semiconductor chips on a semiconductor substrate using electrical properties thereof, the method comprising making an identification mark on a reference semiconductor chip before sorting the semiconductor chips.

13. The method of claim 12, wherein making the identification mark comprises illuminating a laser on the reference semiconductor chip.

14. The method of claim 13, wherein illuminating the laser comprises adjusting the focus size of the laser according to the area of the reference semiconductor chip.

15. The method of claim 13, wherein illuminating the laser comprises transforming a surface of the reference semiconductor chip.

16. The method of claim 12, wherein making the identification mark comprises making a laser mark for identification on the reference semiconductor chip.

17. A semiconductor substrate, comprising:

a plurality of semiconductor chips arranged in the form of a matrix; and

an identification mark made on a reference semiconductor chip of the plurality of semiconductor chips.

18. The semiconductor substrate of claim 17, wherein the identification mark is a laser mark.

19. The semiconductor substrate of claim 17, wherein the identification mark is formed by thermally hardening a surface layer of the reference semiconductor chip.

20. The semiconductor substrate of claim 17, wherein the reference semiconductor chip is the first semiconductor chip when assembling the semiconductor chips.