High-density inter-die interconnect structure

• US 20060166395A1
• Filed: 03/29/2006
• Published: 07/27/2006
• Est. Priority Date: 09/10/2001
• Status: Abandoned Application

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Inventors: McMacken, John Russell, Layman, Paul Arthur
• Application Number:
  US11/392,375
• Publication Number:
  US 20060166395A1
• Time in Patent Office: Days
• US Class Current: 438/60
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01058 Cerium [Ce]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

Claims

1. A method for fabricating an image sensing and processing system, comprising:

fabricating a first integrated circuit comprising a plurality of image sensing elements responsive to electromagnetic radiation incident on a first surface of the first integrated circuit;

fabricating a plurality of first conductive interconnect elements in electrical communication with one or more of the plurality of image sensing elements, wherein the plurality of first interconnect elements are disposed on a second surface of the first integrated circuit;

fabricating a second integrated circuit comprising a plurality of image processing elements;

fabricating a plurality of second conductive interconnect elements in electrical communication with one or more of the plurality of image processing elements;

wherein a pitch of two or more of the plurality of first interconnect elements is substantially equal to a pitch of two or more of the plurality of second interconnect elements; and

positioning one or more of the plurality of first interconnect elements in electrical communication with one or more of the plurality of second interconnect elements.

2. The method of claim 1 wherein the step of fabricating the plurality of first interconnect elements comprises forming a plurality of conductive bumps on the second surface, the step of fabricating the plurality of second interconnect elements comprises forming a plurality of conductive pads and the step of positioning comprises attaching one or more of the plurality of conductive bumps to one or more of the plurality of conductive pads.

3. The method of claim 1 wherein the step of fabricating the plurality of image sensing elements comprises doping regions of a substrate of a first conductivity type with a dopant of a second conductivity type.

4. The method of claim 1 wherein the step of fabricating the first integrated circuit comprises fabricating the first integrated circuit according to a first fabrication process and the step of fabricating the second integrated circuit comprises fabricating the second integrated circuit according to a second fabrication process different from the first fabrication process.

5. The method of claim 4 wherein the first process is optimized for forming the plurality of image sensing elements and the second process is optimized for forming the plurality of image processing elements.

6. The method of claim 1 wherein the first surface of the first integrated circuit is substantially parallel to the second surface of the first integrated circuit.

7. The method of claim 1 wherein the plurality of image sensing elements comprises a plurality of independently operable image sensing elements for collectively forming an image of a scene in response to electromagnetic radiation reflected from the scene toward the first surface.

8. The method of claim 1 wherein a number of the plurality of image sensing elements equals a number of the plurality of first interconnect elements.

9. The method of claim 1 wherein the step of fabricating the first integrated circuit further comprises fabricating the plurality of image sensing elements in an array or in a linear orientation.

10. The method of claim 1 wherein the step of fabricating the first integrated circuit comprises fabricating the first integrated circuit with a first surface to maximize the electromagnetic radiation received by the plurality of image sensing elements.

11. The method of claim 1 wherein the step of fabricating the first integrated circuit comprises fabricating the first integrated circuit to maximize a fill factor of the plurality of image sensing elements on the first surface.

12. A method for sensing and processing light image signals, comprising:

providing light signals to a first surface of a first semiconductor die;

producing electrical signals in the first semiconductor die in response to the light signals;

communicating the electrical signals to a second surface of the first semiconductor die;

forming an electrical connection between first conductive elements on the second surface of the first semiconductor die and second conductive elements on a first surface of a second semiconductor die for providing the electrical signals to the second die, wherein a pitch of the first conductive elements is substantially equal to a pitch of the second conductive elements; and

processing the electrical signals in the second die.

13. The method of claim 12 wherein the step of forming the electrical connection further comprises:

forming the first conductive elements on the second surface of the first semiconductor die;

forming the second conductive elements on the first surface of the second semiconductor die; and

attaching the first and the second conductive elements to form the electrical connection.

14. The method of claim 13 wherein the step of forming the first conductive elements comprises forming conductive bumps, and wherein the step of forming the second conductive elements comprises forming conductive pads.

15. The method of claim 12 wherein the step of producing the electrical signals further comprises producing electrical signals from each one of a plurality of substantially similar image sensors formed in the first die according to a first fabrication process, and wherein the second die comprises signal processing elements formed according to a second fabrication process different from the first fabrication process.

16. The method of claim 15 wherein an electrical signal produced by each one of the plurality of image sensors is communicated to one of the first conductive elements.

17. The method of claim 15 wherein the plurality of image sensors are formed in the first semiconductor die to maximize the response of the image sensors to the light signals.

18. The method of claim 15 wherein each one of the plurality of image sensors comprises a region of a first dopant type and a region of a second dopant type.

19. The method of claim 12 wherein the first surface of the first semiconductor die is substantially parallel to the second surface thereof.