Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process

• US 20060166491A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Ida, Kensaku
• Application Number:
  US11/040,780
• Publication Number:
  US 20060166491A1
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence

Abstract

A method of fabricating dual damascene interconnections begins by forming on a substrate a dielectric layer by a PECVD process that employs a first precursor gas. A capping layer is formed on the dielectric layer by a PECVD process that also employs the first precursor gas such that deposition of the dielectric layer and the capping layer are performed in a continuous manner without deactivation of a plasma. A via is formed in the capping layer and the dielectric layer. The dielectric layer is partially etched to form a trench, which is connected to the via and in which interconnections will be formed. The interconnections are completed by filling the trench and the via with copper.

Claims

1. A method of fabricating dual damascene interconnections, the method comprising:

(a) forming on a substrate a dielectric layer by a PECVD process that employs a first precursor gas;

(b) forming a capping layer on the dielectric layer by a PECVD process that employs said first precursor gas such that deposition in steps (a) and (b) are performed in a continuous manner without deactivation of a plasma;

(c) forming a via in the capping layer and the dielectric layer;

(d) partially etching the dielectric layer to form a trench, which is connected to the via and in which interconnections will be formed; and

(e) completing interconnections by filling the trench and the via with copper.

2. The method of claim 1 wherein the fist precursor gas is an organosilicon material.

3. The method of claim 1 wherein the organosilicon material is octamethylcycloterasiloxane, (OMCTS).

4. The method of claim 1 wherein the organosilicon material is 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS).

5. The method of claim 1 wherein step (b) further comprises the step of selectively adjusting at least one process parameter employed in the PECVD process from that used in step (a).

6. The method of claim 5 wherein said at least one process parameter is selected from the group consisting of a gas flow rate and a plasma characteristic.

7. The method of claim 6 wherein said plasma characteristic comprises a plasma gas pressure.

8. The method of claim 6 wherein said plasma characteristic comprises an RF power level.

9. The method of claim 5 wherein said at least one process parameter comprises a ratio of the precursor gas to O₂ that is introduced during the PECVD process.

10. The method of claim 9 wherein the precursor gas is octamethylcyclotetrasiloxane, (OMCTS).

11. The method of claim 1 further comprising, before step (a):

forming a lower interconnection on the substrate; and

forming an etch stop layer on the lower interconnection.

12. The method of claim 11 wherein the step of forming the etch stop layer is performed by a PECVD process that employs said first precursor gas such that deposition of the etch stop layer and the dielectric layer is performed in a continuous manner without deactivation of the plasma.

13. The method of claim 1 further comprising the step of forming a barrier layer overlying the via and the trench prior to filling the trench and the via with copper;

14. The method of claim 13 wherein the barrier layer is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium silicide or zircuonium.

15. The method of claim 1, wherein step (c) comprises:

forming a photoresist pattern on the capping layer to define the via; and

etching the capping layer and the dielectric layer using the photoresist pattern as an etch mask.

16. The method of claim 1, wherein step (d) includes:

forming a trench photoresist pattern on the capping layer to define the trench;

forming the trench by etching using the trench photoresist pattern as an etch mask.

17. An integrated circuit having a dual damascene interconnection constructed in accordance with the method of claim 1.