Memory hub system and method having large virtual page size

• US 20060168407A1
• Filed: 01/26/2005
• Published: 07/27/2006
• Est. Priority Date: 01/26/2005
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Stern, Bryan Alan
• Application Number:
  US11/044,919
• Publication Number:
  US 20060168407A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory system and method includes a memory hub controller coupled to a plurality of memory modules through a high-speed link. Each of the memory modules includes a memory hub coupled to a plurality of memory devices. The memory hub controller issues a command to open a page in a memory device in one memory module at the same time that a page is open in a memory device in another memory module. In addition to opening pages of memory devices in two or more memory modules, the pages that are simultaneously open may be in different ranks of memory devices in the same memory module and/or in different banks of memory cells in the same memory device. As a result, the memory system is able to provide an virtual page having a very large effective size.

Claims

1. A memory system, comprising:

a plurality of memory modules, each of the memory modules including a memory hub coupled to a plurality of memory devices; and

a memory hub controller coupled to the memory hub in each of the memory modules through a high-speed link, the memory hub controller being operable to issue a command to one of the memory modules to open a page in one of the memory devices in the memory module at the same time that a page is open in one of the memory devices in another one of the memory modules.

2. The memory system of claim 1 wherein the memory devices in each of the memory modules are divided into at least two ranks, and wherein the memory hub controller is operable to issue a command to a memory hub to open a page in one rank of the memory devices at the same time that a page is open in another rank of the memory devices in the same memory module.

3. The memory system of claim 1 wherein the memory devices in each of the memory modules include a plurality of banks of memory cells, and wherein the memory hub controller is operable to issue a command to a memory hub to open a page in one of the banks of memory cells at the same time that a page is open in another rank of the memory devices in the same memory module.

4. The memory system of claim 1 wherein the memory hub controller is operable to provide an address corresponding to a first row address with the command to open a page in one of the memory devices, and wherein the memory hub controller is operable to provide an address corresponding to a second row address when providing the command to open a page in the other one of the memory modules.

5. The memory system of claim 4 wherein the first row address is identical to the second row address.

6. The memory system of claim 1 wherein the high-speed link comprises a high-speed downlink coupling the commands from the memory hub controller to the memory modules and a high-speed uplink coupling read data from the memory modules to the memory hub controller.

7. The memory system of claim 1 wherein the memory hub in at least some of the memory modules comprises:

a first receiver coupled to a portion of the downlink extending from the memory hub controller;

a first transmitter coupled to a portion of the uplink extending to the memory hub controller;

a second receiver coupled to a portion of the uplink extending from a downstream memory module;

a second transmitter coupled to a portion of the downlink extending toward the downstream memory module;

a memory hub local coupled to the first receiver, the first transmitter, and the memory devices in the memory module,

a downstream bypass link coupling the first receiver to the second transmitter; and

an upstream link coupling the second receiver to the first transmitter.

8. The memory system of claim 1 wherein the memory devices in each of the memory modules comprise dynamic random access memory devices.

9. A processor-based system, comprising

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;

a plurality of memory modules, each of the memory modules including a memory hub coupled to a plurality of memory devices; and

a memory hub controller coupled to the processor through the processor bus and to the memory hub in each of the memory modules through a high-speed link, the memory hub controller being operable to issue a command to one of the memory modules to open a page in one of the memory devices in the memory module at the same time that a page is open in one of the memory devices in another one of the memory modules.

10. The processor-based system of claim 9 wherein the memory devices in each of the memory modules are divided into at least two ranks, and wherein the memory hub controller is operable to issue a command to a memory hub to open a page in one rank of the memory devices at the same time that a page is open in another rank of the memory devices in the same memory module.

11. The processor-based system of claim 9 wherein the memory devices in each of the memory modules include a plurality of banks of memory cells, and wherein the memory hub controller is operable to issue a command to a memory hub to open a page in one of the banks of memory cells at the same time that a page is open in another rank of the memory devices in the same memory module.

12. The processor-based system of claim 9 wherein the memory hub controller is operable to provide an address corresponding to a first row address with the command to open a page in one of the memory devices, and wherein the memory hub controller is operable to provide an address corresponding to a second row address when providing the command to open a page in the other one of the memory modules.

13. The processor-based system of claim 12 wherein the first row address is identical to the second row address.

14. The processor-based system of claim 9 wherein the high-speed link comprises a high-speed downlink coupling the commands from the memory hub controller to the memory modules and a high-speed uplink coupling read data from the memory modules to the memory hub controller.

15. The processor-based system of claim 9 wherein the memory hub in at least some of the memory modules comprises:

a first receiver coupled to a portion of the downlink extending from the memory hub controller;

a first transmitter coupled to a portion of the uplink extending to the memory hub controller;

a second receiver coupled to a portion of the uplink extending from a downstream memory module;

a second transmitter coupled to a portion of the downlink extending toward the downstream memory module;

a memory hub local coupled to the first receiver, the first transmitter, and the memory devices in the memory module,

a downstream bypass link coupling the first receiver to the second transmitter; and

an upstream link coupling the second receiver to the first transmitter.

16. The processor-based system of claim 9 wherein the memory devices in each of the memory modules comprise dynamic random access memory devices.

17. In a memory system having memory hub controller coupled to a first and second memory modules each of which includes a plurality of memory devices, a method of accessing the memory devices in the memory modules, comprising:

opening a page in at least one of the memory devices in the first memory module;

opening a page in at least one of the memory devices in the second memory module while the page in the at least one of the memory devices in the first memory module remains open; and

accessing the open pages in the memory devices in the first and second memory modules.

18. The method of claim 17 wherein the acts of opening a page in at least one of the memory devices in the first memory module and opening a page in at least one of the memory devices in the second memory module comprise activating a row of memory cells in the at least one of the memory devices in the first and second memory modules.

19. The method of claim 17 wherein the act of opening a page in at least one of the memory devices in the first memory module comprise opening a page in a first bank of the at least one of the memory devices while a page in a second bank of the at least one of the memory devices is open.

20. The method of claim 17 wherein the memory devices in the first memory module are divided into first and second ranks, and wherein the act of opening a page in at least one of the memory devices in the first memory module comprise opening a page in at least one of the memory devices in the first rank while a page in at least one of the memory devices in the second rank is open.

21. The method of claim 17 wherein the act of accessing the open pages in the memory devices in the first and second memory modules comprises accessing the open page in the memory devices in the first memory module while a new page in at least one of the memory devices in the second memory module is being opened.

22. The method of claim 17 wherein the act of accessing the open pages in the memory devices in the first and second memory modules comprises accessing the open page in the memory devices in the first memory module while a new page in at least one of the memory devices in the second memory module is being precharged.

23. The method of claim 17 wherein the acts of opening a page in at least one of the memory devices in the first memory module and opening a page in at least one of the memory devices in the second memory module comprise opening a page in a memory device in the second memory module having the same row addresses as the page that is opened in the memory device in the first memory module.