Random access memory having low initial latency

• US 20060168417A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Loffler, Steffen
• Granted Patent: US 7,401,179 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0879 Burst mode
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A random access memory comprises an array of memory cells and a controller. The controller is configured to access the array of memory cells in a double data rate prefetch mode in response to a read command and in a single data rate mode after the first double data rate access is completed.

Claims

1. A random access memory comprising:

an array of memory cells; and

a controller configured to access the array of memory cells in a double data rate prefetch mode in response to a read command and in a single data rate mode after the first double data rate access is completed.

2. The random access memory of claim 1, wherein the controller is configured to prefetch 2n data bits in response to a read command.

3. The random access memory of claim 2, wherein n equals 16.

4. The random access memory of claim 1, wherein the controller is configured to provide an initial asynchronous column address strobe to access the array of memory cells in the double data rate prefetch mode and synchronous column address strobes to access the array of memory cells in the single data rate mode.

5. A pseudo-static random access memory comprising:

an array of memory cells; and

a memory controller configured to;

asynchronously prefetch a first data word and a second data word from the array of memory cells in response to a read command; and

synchronously retrieve a third data word from the array of memory cells after asynchronously prefetching the first and second data words.

6. The pseudo-static random access memory of claim 5, wherein the memory controller is configured to provide an asynchronous column address strobe to initiate the asynchronous prefetch of the first data word and the second data word and provide a synchronous column address strobe to initiate the synchronous retrieval of the third data word.

7. The pseudo-static random access memory of claim 5, further comprising:

a data in/out circuit configured to output the first data word in response to a first rising edge of a clock signal, output the second data word in response to a second rising edge of the clock signal, and output the third data word in response to a third rising edge of the clock signal.

8. A pseudo-static random access memory for a cellular phone comprising:

a memory block;

a first data output control block configured to receive a lower n data bits from the memory block in response to a first signal and a third signal;

a second data output control block configured to receive an upper n data bits from the memory block in response to the first signal;

a multiplexer configured to selectively output one of the lower n data bits and the upper n data bits based on a second signal; and

a command block configured to provide the first signal in response to a read command, the second signal in response to a first rising edge of a clock signal after the first signal, and the third signal in response to a second rising edge of the clock signal after the first signal.

9. The pseudo-static random access memory of claim 8, wherein the first signal comprises an asynchronous column address strobe signal.

10. The pseudo-static random access memory of claim 8, wherein the second signal comprises a missing second column address strobe signal.

11. The pseudo-static random access memory of claim 8, wherein the third signal comprises a synchronous column address strobe signal.

12. The pseudo-static random access memory of claim 8, wherein the memory block comprises an array of dynamic random access memory cells.

13. A pseudo-static random access memory comprising:

means for receiving a read command;

means for issuing an asynchronous column address strobe in response to the read command;

means for prefetching a first data word and a second data word from a memory array in response to the asynchronous column address strobe;

means for issuing a synchronous column address strobe after the asynchronous column address strobe; and

means for retreiving a third data word from the memory array in response to the synchronous column address strobe.

14. The pseudo-static random access memory of claim 13, further comprising:

means for outputting the first data word in response to a first rising edge of a clock signal after the asynchronous column address strobe;

means for outputting the second data word in response to the second rising edge of the clock signal after the asynchronous column address strobe; and

means for outputting the third data word in response to the third rising edge of the clock signal after the asynchronous column address strobe.

15. A method for accessing a memory, the method comprising:

receiving a read command;

issuing an asynchronous column address strobe in response to the read command;

prefetching a first data word and a second data word from a memory array in response to the asynchronous column address strobe;

issuing a synchronous column address strobe after issuing the asynchronous column address strobe; and

retreiving a third data word from the memory array in response to the synchronous column address strobe.

16. The method of claim 15, further comprising:

outputting the first data word in response to a first rising edge of a clock signal after the asynchronous column address strobe;

outputting the second data word in response to the second rising edge of the clock signal after the asynchronous column address strobe; and

outputting the third data word in response to the third rising edge of the clock signal after the asynchronous column address strobe.

17. The method of claim 15, wherein issuing the synchronous column address strobe comprises issuing the synchronous column address strobe more than one clock cycle after issuing the asynchronous column address strobe.

18. The method of claim 15, wherein prefetching the first data word and the second data word from the memory array comprises prefetching a first 16 bit data word and a second 16 bit data word from the memory array.

19. The method of claim 15, wherein retrieving the third data word from the memory array comprises retrieving a third 16 bit data word from the memory array.

20. A method for reading a pseudo-static random access memory, the method comprising:

receiving a read command;

prefetching a first data word and a second data word from a memory array in a double data rate mode in response to the read command;

outputting the first data word in response to a first rising edge of a clock signal;

outputting the second data word in response to a second rising edge of the clock signal;

retreiving a third data word from the memory array in a single data rate mode in response to the second rising edge of the clock signal; and

outputting the third data word in response to a third rising edge of the clock signal.

21. The method of claim 20, further comprising:

asynchronously decoding the read command.

22. The method of claim 20, further comprising:

issuing an asynchronous column address strobe in response to the read command; and

wherein prefetching the first data word and the second data word from the memory array comprises prefetching the first data word and the second data word from the memory array in response to the asynchronous column address strobe.

23. The method of claim 22, further comprising:

issuing a synchronous column address strobe in response to the second rising edge of the clock signal; and

wherein retreiving the third data word from the memory array comprises retreiving the third data word from the memory array in response to the synchronous column address strobe.

24. A method for reading a CellularRAM, the method comprising:

receiving a read command;

issuing an asynchronous column address strobe signal in response to the read command;

reading a first data word and a second data word in parallel from a memory array in response to the asynchronous column address strobe;

outputting the first data word in response to a first rising edge of a clock signal;

outputting the second data word in response to a second rising edge of the clock signal;

issuing a synchronous column address strobe in response to the second rising edge of the clock signal;

reading a third data word from the memory array in response to the synchronous column address strobe; and

outputting the third data word in response to a third rising edge of the clock signal.

25. The method of claim 24, wherein issuing the synchronous column address strobe comprises issuing the synchronous column address strobe more than one clock cycle after issuing the asynchronous column address strobe.