Method and system for testing RAM redundant integrated circuits

• US 20060168488A1
• Filed: 01/26/2005
• Published: 07/27/2006
• Est. Priority Date: 01/26/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hill, J. Michael, Newsome, David Thomas, Mellinger, Todd
• Granted Patent: US 7,284,168 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.

Claims

1. Method of production testing a random access memory (RAM) redundant integrated circuit die fabricated on a wafer, said method comprising the steps of:

at the wafer level,

testing said RAM redundant integrated circuit die;

identifying a failed element of the redundant RAM of said integrated circuit die; and

replacing said failed element with a redundant element in the redundant RAM of said integrated circuit die;

thereafter, sectioning said tested die from the wafer;

packaging said sectioned die in an integrated circuit package;

at the package level,

performing a test on said packaged integrated circuit die;

identifying a failed element of the redundant RAM of said integrated circuit die; and

replacing said failed element with a redundant element in the redundant RAM of said integrated circuit die.

2. The method of claim 1 wherein the steps of performing, identifying and replacing at the package level are repeated.

3. The method of claim 1 including repeating the steps of performing, identifying and replacing at the package level as long as there is a failed element identified after test.

4. The method of claim 1 including repeating the steps of performing, identifying and replacing at the package level until there is no redundant element left in the redundant RAM to replace a failed element.

5. The method of claim 1 wherein the step of replacing at the package level comprises electrically blowing fuses in the redundant RAM of the integrated circuit die to replace the failed element with a redundant element.

6. The method of claim 1 wherein the step of replacing at the wafer level comprises electrically blowing fuses in the redundant RAM of the integrated circuit die to replace the failed element with a redundant element.

7. The method of claim 1 wherein the step of replacing at the wafer level comprises replacing a failed row of storage cells with a redundant row of storage cells in the redundant RAM of the integrated circuit die.

8. The method of claim 1 wherein the step of replacing at the wafer level comprises replacing a failed column of storage cells with a redundant column of storage cells in the redundant RAM of the integrated circuit die.

9. The method of claim 1 wherein the step of replacing at the package level comprises replacing a failed row of storage cells with a redundant row of storage cells in the redundant RAM of the integrated circuit die.

10. The method of claim 1 wherein the step of replacing at the package level comprises replacing a failed column of storage cells with a redundant column of storage cells in the redundant RAM of the integrated circuit die.

15. The method of claim 11 wherein the step of replacing comprises electrically blowing fuses in the redundant RAM of the packaged integrated circuit die to replace the failed element with a redundant element.

16. The method of claim 11 wherein the step of replacing comprises replacing a failed row of storage cells with a redundant row of storage cells in the redundant RAM of the integrated circuit die.

17. The method of claim 11 wherein the step of replacing comprises replacing a failed column of storage cells with a redundant column of storage cells in the redundant RAM of the integrated circuit die.

11. Method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising:

identifying a failed element in the redundant RAM of said packaged integrated circuit die; and

replacing said failed element with a redundant element in the redundant RAM of said packaged integrated circuit die.

12. The method of claim 11 wherein the steps of identifying and replacing are repeated.

13. The method of claim 11 including repeating the steps of identifying and replacing as long as there is a failed element in the redundant RAM of said packaged integrated circuit die.

14. The method of claim 11 including repeating the steps of identifying and replacing until there is no redundant element left in the redundant RAM to replace a failed element.

18. System for testing a packaged random access memory (RAM) redundant integrated circuit die comprising:

a tester unit coupled to said packaged integrated circuit die and operative to identify a failed element in the redundant RAM of said packaged integrated circuit die; and

a programmer coupled to said tester unit and packaged integrated circuit die and operative to replacing said failed element with a redundant element in the redundant RAM of said packaged integrated circuit die.

19. The system of claim 18 wherein the programmer is operative to electrically blow fuses in the redundant RAM of the packaged integrated circuit die to replace the failed element with a redundant element.

20. The system of claim 18 wherein the programmer is integral to the tester unit.

21. System for testing a packaged random access memory (RAM) redundant integrated circuit die comprising:

means for identifying a failed element in the redundant RAM of said packaged integrated circuit die; and

means for replacing said failed element with a redundant element in the redundant RAM of said packaged integrated circuit die.