Systems and methods for mitigating latency associated with error detection and correction

• US 20060168503A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Gostin, Gary B., Schroeder, Michael A., Brueggen, Christopher Michael
• Granted Patent: US 7,577,890 B2
• Time in Patent Office: Days
• US Class Current: 714/798
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.

Claims

1. A system for mitigating latency associated with error detection and correction of a data structure, the system comprising:

a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure; and

an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.

2. The system of claim 1, wherein the EDC component sequentially performs error detection and correction on each of a given code word of a plurality of code words forming the data structure in response to a request for the data structure.

3. The system of claim 2, wherein the packet generator begins transmitting data associated with a given code word in the response packet as the EDC component determines that the given code word does not have errors.

4. The system of claim 3, wherein the packet generator transmits dummy data associated with a given code word in the response packet if the EDC component determines that the given code word has an error, the packet generator transmits valid data once the data associated with the given code word has been corrected.

5. The system of claim 2, wherein a first code word of the plurality of code words includes the tag portion, the EDC component forwarding a copy of the tag portion to facilitate building of the response packet by the packet generator concurrently with the error detection and correction.

6. The system of claim 1, wherein the packet generator builds a header portion of the response packet based on the tag portion of the data structure.

7. The system of claim 1, wherein the response packet is one of a data packet and a request packet.

8. The system of claim 1, wherein the EDC component provides a speculative status indicator to the packet generator, the speculative status indicator informing the packet generator if an error has been detected in at least a portion of the data structure.

9. The system of claim 1, wherein the packet generator aborts packet generation of the response packet if an error has been detected in the data structure and the response packet is a data packet, and transmits the response packet if the speculative status indicator informs the packet generator that an error has not been detected in the data structure.

10. The system of claim 1, wherein the packet generator builds at least a portion of a response packet based on speculative data associated with the data structure to mitigate latency associated with error detection and correction.

11. The system of claim 1, further comprising a cache coherency controller that receives a tag portion of the data structure and issues a command to the packet generator to build one of a request packet and a data packet based on the tag portion.

12. The system of claim 11, wherein the cache coherency controller maintains a state control structure that maintains status indicators associated with issued commands, the status indicators provide an indication of whether a given issue command is based on one of speculative data and known correct data.

13. The system of claim 1, further comprising a data storage that stores data associated with the data structure for transmitting with a data packet, wherein the data stored in the data storage includes at least one of speculative data and correct data.

14. The system of claim 1, further comprising a data storage that stores data associated with the data structure for transmitting with a data packet, wherein the data stored in the data storage includes at least one of speculative data and correct data.

15. The system of claim 1, further comprising a plurality of distributed control logic blocks operative to control the data flow and handshaking between components in the system.

16. The system of claim 1, being a multi-processor system.

17. A memory system comprising:

an error detection and correction (EDC) component that detects and corrects errors in given code word associated with a data structure formed from a plurality of code words;

a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure residing in a first code word of the plurality of code words; and

a plurality of memory devices that store the data structure based on a given memory address, and provide the EDC component the plurality of code words in response to a request for the data structure;

wherein the EDC component receives the plurality of code words in a sequential manner and forwards a copy of the tag portion from the first code word to facilitate the building of a response packet by the packet generator concurrently with the error detection and correction of the data structure.

18. The system of claim 17, further comprising a cache coherency controller that receives the tag portion and issues a command to the packet generator to build one of a request packet and a data packet based on the tag portion.

19. The system of claim 18, wherein the cache coherency controller maintains a state control structure that maintains status indicators associated with issued commands, the status indicators provide an indication of whether a given issue command is based on one of speculative data and known correct data.

20. The system of claim 17, wherein the EDC component provides a speculative status indicator to the packet generator, the speculative status indicator informing the packet generator if an error has been detected in at least a portion of the data structure.

21. The system of claim 20, wherein the packet generator aborts packet generation of the response packet if an error has been detected in at least the tag portion of the data structure.

22. The system of claim 17, further comprising a data storage that stores data associated with the data structure for transmitting with a data packet, wherein the data stored in the data storage includes at least one of speculative data and known correct data.

23. A system for correcting errors in a data structure in response to a request for the data structure, the system comprising:

means for performing error detection and correction on a data structure that includes a tag portion;

means for issuing a command to build a response packet based on the tag portion; and

means for building a response packet based on the issue command concurrently with the error detection and correction on the data structure.

24. The system of claim 23, wherein the means for performing error detection and correction forwards a copy of the tag portion to the means for issuing in response to receiving at least the tag portion of the data structure to facilitate concurrent building of a response packet associated with the data structure with error detection and correction of the data structure.

25. The system of claim 23, further comprising means for providing an indication if an error has been detected in at least the portion of the data structure to the means for building a response packet, the means for building a response packet aborting building of the response packet if an error is detected in at least the tag portion of the data structure, and building a new response packet based on known correct data associated with the data structure.

26. A method for mitigating latency associated with error detection and correction of a data structure, the method comprising:

providing a data structure in response to a request for the data structure, the data structure having a tag portion;

building a response packet based on the tag portion; and

performing error detection and correction on the data structure concurrently with the building of the response packet.

27. The method of claim 26, wherein the building a response packet comprises building one of a request packet and a data packet.

28. The method of claim 26, further comprising transmitting the response packet if no errors are detected in the data structure.

29. The method of claim 26, wherein the performing error detection and correction comprises performing error detection on each of a given code word of a plurality of code words forming the data structure, a first code word of the plurality of code words containing the tag portion.

30. The method of claim 29, further comprising aborting the building of the response packet if an error has been detected in the first code word.

31. The method of claim 26, further comprising aborting the building of the response packet if an error has been detected in the data structure and the response packet is a data packet.

32. A method for mitigating latency associated with a data request, the method comprising:

providing a plurality of code words forming a data structure in sequential order, a first code word provided of the plurality of code words having a tag portion;

building a header of a response packet based on the tag portion;

performing error detection and correction on the plurality of code words in sequential order concurrently with the building of the header; and

transmitting the response packet with data associated with a given code word that has been determined to be without errors concurrently with the performing of error detection and correction on a subsequent code word.

33. The method of claim 32, further comprising transmitting dummy data in the response packet in place of data associated with a subsequent code word that has been determined to have an error, and transmitting corrected data associated with the subsequent code word once the data associated with the subsequent code word has been corrected.

34. The method of claim 33, further comprising providing an invalid flag with the transmitting of the dummy data, and a valid flag with the transmitting of the corrected data.