Substrate mapping

• US 20060168552A1
• Filed: 03/22/2006
• Published: 07/27/2006
• Est. Priority Date: 08/22/2001
• Status: Abandoned Application

• Current Assignee: Derek J. Gochnour, Warren M. Farnworth
• Original Assignee: Derek J. Gochnour, Warren M. Farnworth
• Inventors: Farnworth, Warren M., Gochnour, Derek J.
• Application Number:
  US11/386,474
• Publication Number:
  US 20060168552A1
• Time in Patent Office: Days
• US Class Current: 716/126
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/53043 including means to divert defective work part
• CPC Class Codes: Y10T 29/53178 Chip component
• CPC Class Codes: Y10T 29/53187 Multiple station assembly apparatus

Abstract

A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.

Claims

1. An evaluation method for die sites of a substrate comprising:

locating good die sites and defective die sites of the substrate; and

storing information for the good die sites and the defective die sites of the substrate in an electronic file for accessing information of at least one good die site on the substrate and for accessing information for at least one defective die site on the substrate for attaching at least one semiconductor die to the substrate to a good die site of the good die sites and attaching a known defective die to a defective die site of the defective die sites.

2. A semiconductor package fabrication method for a semiconductor package having a substrate having a plurality of die sites comprising:

recording information for good die sites and defective die sites on the substrate;

using the information for attaching at least one known good semiconductor die to a good die site on the substrate while attaching a known defective die to a defective die site of the substrate; and

encapsulating the substrate using an encapsulation material for encapsulating at least one known good die on the substrate.

3. A substrate comprising:

a substrate having encoded information thereon comprising information uniquely identifying said substrate at a peripheral portion of the substrate, a first surface and a second surface, at least one of said first surface and said second surface including a plurality of pretested die sites, each of said pretested die sites determined to be one of a good die site and a defective die site; and

at least one pretested good die site and at least one pretested defective die site used for attaching at least one pretested know good die to a pretested good die site and at least one defective die to at least one pretested defective die site.

4. A system for assembling a semiconductor package comprising:

a substrate having a plurality of die sites having encoded information thereon;

a reading unit connected to an electronic file for reading the encoded information, the electronic file having mapped information of said mounting substrate including locations good die attach sites and defective die attach sites;

an attachment apparatus connected to the reading unit and the electronic file for using at least one of the reading unit and the electronic file providing the mapped information to the attachment apparatus for selectively attaching at least one good die to a good die site and selectively attaching at least one defective die to a defective die site.

5. A semiconductor package comprising:

a substrate having encoded good die sites and encoded defective die sites; and

at least one known good die attached to an encoded good die site and at least one defective die attached to an encoded defective die site.