Thin film transistor array panel

• US 20060169984A1
• Filed: 01/19/2006
• Published: 08/03/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Moon, Kook-Chul, Joo, Soong-Yong, Park, Tae-Hyeong, Kim, Il-Gon
• Granted Patent: US 7,612,377 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film transistor array panel is provided. The array panel includes a storage capacitance that is substantially uniform, and allows for a relatively large capacitance in a relatively small area. In some embodiments, the panel includes: a substrate; a plurality of semiconductor regions on the substrate, including a plurality of source and drain regions doped with a first impurity type and a dummy region doped with a second impurity type, and an intrinsic region having storage and channel regions; a gate insulating layer covering at least a portion of the semiconductor regions; a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer; a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer; a data line including a source electrode connected to the source region and formed on the gate insulating layer; a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and a pixel electrode connected to the drain electrode.

Claims

1. A thin film transistor array panel comprising:

a substrate;

a plurality of semiconductor regions on the substrate, the semiconductor regions including a plurality of source and drain regions doped with a first impurity type, a dummy region doped with a second different impurity type, and an intrinsic region having storage and channel regions;

a gate insulating layer covering at least a portion of the semiconductor regions;

a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer;

a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer;

a data line including a source electrode connected to the source region and formed on the gate insulating layer;

a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and

a pixel electrode connected to the drain electrode.

2. The thin film transistor array panel of claim 1, wherein one of the first impurity type and the second impurity type is N-type and the other is P-type.

3. The thin film transistor array panel of claim 2, wherein the drain electrode at least partially overlaps the storage electrode.

4. The thin film transistor array panel of claim 2, further comprising:

a blocking layer formed between the substrate and the semiconductor regions.

5. The thin film transistor array panel of claim 1, further comprising:

one or more lightly doped regions disposed between the source and the drain region and the channel region.

6. The thin film transistor array panel of claim 5, wherein the storage region is positioned between the drain region and the dummy region.

7. A display panel comprising:

a storage region;

a dummy region positioned adjacent the storage region on a first side of the storage region, the dummy region doped with impurities of a first impurity type;

a transistor region positioned adjacent the storage region on a second side of the storage region, the transistor region doped with impurities of a second impurity type different than the first impurity type;

a storage electrode at least partially overlapping the storage region and separated from the storage region by a dielectric region;

a transistor electrode connected to the transistor region and the dummy region, the transistor electrode at least partially overlapping the storage electrode and separated from the storage electrode by a dielectric region;

a pixel electrode region connected to the transistor electrode; and

wherein a storage capacitor comprises the storage electrode, the storage region, and the dielectric region separating the storage electrode from the storage region.

8. The display panel of claim 7, wherein the first impurity type is P-type and the second impurity type is N-type.

9. The display panel of claim 7, wherein the transistor region comprises a drain region.

10. The display panel of claim 7, wherein in operation a pre-determined voltage is applied to the storage electrode, and wherein in operation an electric field is formed between the dummy region and the storage electrode when a pixel voltage applied to the transistor electrode is higher than the pre-determined voltage.

11. The display panel of claim 7, and wherein in operation a pre-determined voltage is applied to the storage electrode, and wherein in operation an electric field is formed between the transistor region and the storage electrode when a pixel voltage applied to the transistor electrode is lower than the pre-determined voltage.

12. The display panel of claim 7, wherein the transistor electrode substantially overlaps the storage electrode.

13. The display panel of claim 7, further comprising a gate region positioned proximate to the transistor region and separated therefrom by a gate insulating region, and wherein the dielectric separating the storage electrode from the storage region is on the same layer as the gate insulating region.

14. A display comprising:

a display panel, the display panel comprising;

a storage region;

a dummy region positioned adjacent the storage region on a first side of the storage region, the dummy region doped with impurities of a first impurity type;

a transistor region positioned adjacent the storage region on a second side of the storage region, the transistor region doped with impurities of a second impurity type different than the first impurity type;

a storage electrode at least partially overlapping the storage region and separated from the storage region by a dielectric region; and

a transistor electrode connected to the transistor region and the dummy region, the transistor electrode at least partially overlapping the storage electrode and separated from the storage electrode by a dielectric region;

a pixel electrode region connected to the transistor electrode; and

wherein a storage capacitor comprises the storage electrode, the storage region, and the dielectric region separating the storage electrode from the storage region; and

a display material;

the display material positioned proximate to the display panel, the display material including a pixel region positioned and configured to display a pixel image part in response to a signal on the pixel electrode.

15. The display of claim 14, wherein the first impurity type is P-type and the second impurity type is N-type.

16. The display of claim 14, wherein the transistor region comprises a drain region.

17. The display of claim 14, wherein in operation a pre-determined voltage is applied to the storage electrode, and wherein in operation an electric field is formed between the dummy region and the storage electrode when a pixel voltage applied to the transistor electrode is higher than the pre-determined voltage.

18. The display of claim 14, and wherein in operation a pre-determined voltage is applied to the storage electrode, and wherein in operation an electric field is formed between the transistor region and the storage electrode when a pixel voltage applied to the transistor electrode is lower than the pre-determined voltage.

19. The display of claim 14, wherein the transistor electrode substantially overlaps the storage electrode.

20. The display of claim 14, wherein the display material comprises at least one of a liquid crystal display material and an organic light emitting diode material.