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Thin film transistor array panel

  • US 20060169984A1
  • Filed: 01/19/2006
  • Published: 08/03/2006
  • Est. Priority Date: 01/31/2005
  • Status: Active Grant
First Claim
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1. A thin film transistor array panel comprising:

  • a substrate;

    a plurality of semiconductor regions on the substrate, the semiconductor regions including a plurality of source and drain regions doped with a first impurity type, a dummy region doped with a second different impurity type, and an intrinsic region having storage and channel regions;

    a gate insulating layer covering at least a portion of the semiconductor regions;

    a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer;

    a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer;

    a data line including a source electrode connected to the source region and formed on the gate insulating layer;

    a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and

    a pixel electrode connected to the drain electrode.

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