Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
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Abstract
A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.
43 Citations
37 Claims
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1-28. -28. (canceled)
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29. A method of fabricating a trench-gate semiconductor device comprising:
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providing a semiconductor substrate of a first conductivity type;
forming an epitaxial layer of the first conductivity type on the substrate;
forming first and second trenches in the epitaxial layer, the first and second trenches being separated by a mesa;
forming dielectric spacers on the sidewalls of the trenches;
filling a bottom portion of the trenches with a semiconductor material of a second conductivity type;
removing portions of the dielectric spacers above the semiconductor material of the second conductivity type;
forming a dielectric layer on the walls of the trenches above the semiconductor material of the second conductivity type and on the top surface of the semiconductor material of the second conductivity type; and
filling an upper portion of the trenches with a conductive gate material. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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37. A method of fabricating a power MOSFET comprising:
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growing an epitaxial layer on a semiconductor substrate, both said epitaxial layer and said substrate being doped with material of a first conductivity type;
forming a first mask on a surface of said epitaxial layer, said first mask having an opening where a trench is to be formed;
etching said epitaxial layer through said opening in said first mask to form a trench in said epitaxial layer;
forming a first dielectric layer on the sidewalls and a bottom of said trench;
removing a portion of said first dielectric layer on the bottom of said trench;
depositing a second epitaxial layer doped with material of a second conductivity type in a lower portion of said trench so as to form a field shield region;
removing a second portion of said first dielectric layer on the sidewalls of said trench above said second epitaxial layer, thereby forming a dielectric spacers on the sides of said field shield region;
forming a second dielectric layer on the exposed portions of the sidewalls of the trench and on a top surface of said field shield region;
filling said trench with a first polysilicon layer;
removing a portion of said first polysilicon layer such that a surface of said first polysilicon layer is located at a level below a top surface of said first mask, thereby forming a polysilicon gate;
depositing a glass layer on said first mask and said polysilicon gate;
planarizing said glass layer such that a surface of said glass layer is coplanar with the top surface of the first mask, thereby forming a glass plug directly above said polysilicon gate;
removing at least a portion of the first mask;
implanting dopant of the second conductivity type to form a body region in said epitaxial layer;
depositing a second polysilicon layer over a top surface of said glass plug and said epitaxial layer, said second polysilicon layer being doped with material of said first conductivity type;
etching said second polysilicon layer directionally so as to form a polysilicon spacer on a sidewall of said glass plug;
heating said polysilicon spacer so as to cause dopant of said first conductivity type to diffuse from said polysilicon spacer into said epitaxial layer, thereby creating a source region;
depositing a metal layer over said glass plug and said first epitaxial layer;
forming a second mask over said metal layer; and
etching said metal layer through an opening in said second mask to form a source metal section of said metal layer.
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Specification