Self-aligned semiconductor contact structures and methods for fabricating the same

• US 20060170062A1
• Filed: 03/31/2006
• Published: 08/03/2006
• Est. Priority Date: 10/31/2002
• Status: Abandoned Application

• Current Assignee: Chang-Sub Lee, Dong-Gun Park, Jeong-Dong Choe, Seong-Ho Kim, Shin-Ae Lee, Sung-Min Kim
• Original Assignee: Chang-Sub Lee, Dong-Gun Park, Jeong-Dong Choe, Seong-Ho Kim, Shin-Ae Lee, Sung-Min Kim
• Inventors: Lee, Shin-Ae, Kim, Sung-Min, Lee, Chang-Sub, Kim, Seong-Ho, Park, Dong-Gun, Choe, Jeong-Dong
• Application Number:
  US11/395,270
• Publication Number:
  US 20060170062A1
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Claims

1. A method of forming a self-aligned contact comprising:

forming gate electrodes that are spaced apart from each other on a semiconductor substrate;

forming a first liner layer on the semiconductor substrate and the gate electrodes;

forming an interlayer insulation layer over the first liner layer;

forming a contact window having opposing spaced apart sidewalls and a bottom by selectively etching the interlayer insulation layer with respect to the first liner layer;

forming a second liner layer over the interlayer insulation layer and the bottom and sidewalls of the contact window;

forming a buffer insulation layer to extend laterally a distance beyond the second liner layer to overhang in the contact window;

exposing the semiconductor substrate between adjacent gate electrodes by performing an etch back process to remove the buffer insulation layer and the second and first insulation layers at a bottom portion of the contact window; and

filling the contact window with conductive material to thereby substantially and/or entirely fill at least a lower portion of the contact window.

2. The method of claim 1, wherein forming the contact window comprises angling the opposing sidewalls thereof so that the sidewalls travel toward each a distance along at least a portion of a length thereof.

3. The method of claim 1, wherein the first and the second liner layers comprise silicon nitride.

4. The method of claim 1, wherein the interlayer insulation layer comprises an oxide layer having a substantially planar surface, and the buffer insulation layer is formed of an oxide layer having an upper surface formed over the interlayer insulation layer disrupted with recesses formed into respective contact windows.

5. The method of claim 1, wherein in the step of forming the contact window by selectively etching the interlayer insulation layer, is carried out so that an upper portion of a gate electrode is etched as well as the first liner layer thereon.

6. The method of claim 1, wherein in the step of exposing the semiconductor substrate is carried out so that the first and second liner layers on the upper and intermediate portions of the sidewalls of the contact window are protected by the buffer insulation layer but the first and second liner layers on the bottom of the contact window are etched away, and wherein, the buffer insulation layer remains on the upper and intermediate portions of the sidewalls of the contact window to form buffer insulation sidewall spacers while the buffer insulation layer on the bottom of the contact window is etched away.

7. The method of claim 1, wherein, after forming the first liner layer and before forming the interlayer insulation layer, the method further comprises:

forming a sacrificial insulation layer;

exposing an upper portion of a gate electrode by etching back the sacrificial insulation layer leaving residual portions of the sacrificial insulation layer;

forming a metal silicide layer on the exposed upper portion of the gate electrode; and

removing the residual portions of the sacrificial insulation layer.

8. A method of forming a self-aligned contact comprising:

forming gate electrodes that are spaced apart from each other with a plurality of the gate electrodes positioned at a cell array region and at least one gate electrode positioned at a peripheral circuit region of the semiconductor substrate, respectively;

forming a first liner layer over the semiconductor substrate and surfaces of the gate electrodes;

forming a sacrificial insulation layer on the first liner layer in an amount sufficient to cover spaces between the gate electrodes of the cell array region;

etching back the sacrificial insulation layer so as to form temporary sidewall spacers on sidewalls of the at least one gate electrode at the peripheral circuit region;

forming a metal silicide layer at least on the semiconductor substrate exposed adjacent the temporary sidewall spacers;

then

removing the sacrificial insulation layer remaining at the cell array region and the temporary sidewall spacers of the peripheral circuit region;

forming an interlayer insulation layer having a substantially planar top surface;

selectively etching the interlayer insulation layer with respect to the first liner layer to form at least one contact window in the cell array region between adjacent first and second gate electrodes, the contact window having opposing spaced apart sidewalls and a bottom;

forming a second liner layer on the sidewalls and bottom of the contact window;

forming a buffer insulation layer on the second liner layer so that the buffer insulation layer extends a lateral distance into the contact window to leave a gap space in the contact window, the buffer insulation layer having a greater thickness at a top portion of the sidewalls of the contact window than at a lower portion of the sidewalls of the contact window;

exposing the semiconductor substrate between the gate electrodes of the cell array region by performing an etch back process; and

filling at least a lower portion of the contact window with conductive material.

9. The method of claim 8, wherein in the step of forming a contact window by selectively etching the interlayer insulation layer, the first liner layer is etched exposing a selected upper portion of the gate electrodes of the cell array region allowing the selected upper portion of the gate electrodes to be removed by the etching while the lower portion is protected from the etching, thereby generating a gate electrode that has an inclined side profile.

10. The method of claim 8, wherein the exposing step is carried out so that the first and/or second liner layers on the upper, intermediate, and/or lower sidewall portions of the contact window are protected by the buffer insulation layer, but the first and second liner layers on the bottom of the contact window are etched away, and wherein the buffer insulation remains on sidewalls of the upper and intermediate portions of the contact window to form sidewall spacers while the buffer insulation layer on the bottom of the contact window is etched away.

11. The method of claim 8, further comprising,

after forming the gate electrodes:

forming lightly doped impurity diffusion regions in the semiconductor substrate at both sides of the gate electrodes using ion implantation; and

after forming the sidewall spacers, performing a second ion implantation process in the peripheral circuit region to form heavily doped impurity diffusion regions, which are spatially positioned proximate the lightly doped impurity diffusion regions, in the semiconductor substrate, at both sides of the temporary sidewall spacers, so that the heavily doped regions reside a greater distance away from the gate electrode than the lightly doped regions.

12. The method of claim 11, wherein the gate electrodes comprise polysilicon, wherein when in an etch back process the sacrificial insulation layer is removed to expose top portions of the gate electrodes at the cell array region and the peripheral circuit region, and the sacrificial insulation layer remains on the sidewalls of the gate electrodes and on the semiconductor substrate therebetween in the cell array region but is removed with the first liner layer in the peripheral circuit region to expose the semiconductor substrate proximate the sidewall spacers, and wherein a metal silicide layer is concurrently formed on the exposed semiconductor substrate over the heavily doped impurity diffusion regions of the peripheral circuit region and on the exposed top portions of the gate electrodes.

13. The method of claim 8, wherein, after forming the gate electrodes, performing ion implantation to form lightly doped impurity diffusion regions in the semiconductor substrate at both sides of the gate electrodes;

and

after forming the temporary sidewall spacers, performing ion implantation to form heavily doped impurity diffusion regions which terminate into the lightly doped impurity diffusion regions of the peripheral circuit region in the semiconductor substrate at both sides of the temporary sidewall spacers.

14. The method of claim 13, wherein the gate electrodes comprise a double-layered structure of polysilicon and tungsten silicide or of polysilicon and tungsten that are sequentially stacked,

wherein in an etch back process after forming the sacrificial insulation layer, the upper portions of the gate electrodes of the cell region and peripheral circuit region are exposed while the sacrificial insulation layer remains on the sidewalls of the gate electrodes and on the semiconductor substrate therebetween, and

wherein the forming the metal silicide layer comprises forming the metal silicide layeron the semiconductor substrate over the heavily doped impurity diffusion regions of the peripheral circuit area.

15. The method of claim 8, after forming the sacrificial insulation layer and before performing the etch back process, the method further comprises forming a photoresist pattern that covers the top surface of the cell array region.

16. The method of claim 8, after forming the metal silicide layer, further comprising a step of forming a protection liner layer thereover for protecting the metal silicide layer.

17. The method of claim 8, further comprising removing at least a portion of the buffer insulation layer from the contact window before filling the contact window with conductive material.

18. The method of claim 16, wherein the first liner layer, the second liner layer, and the protection liner layer comprise silicon nitride.

19. The method of claim 8, wherein the interlayer insulation layer comprises an oxide that is applied to be substantially continuous over the underlying structure with a planar surface, and wherein the buffer insulation layer comprises an oxide that is configured with a substantially planar upper surface and a recess that extends down into the contact window and provides a gap space therein.

20. A method of forming a self-aligned contact window configured to hold a self-aligned contact pad therein in communication with a semiconductor substrate, comprising:

removing a selected portion of an interlayer insulation layer and then an underlying upper portion of adjacent sidewalls of first and second gate electrodes held proximate to each other on a semiconductor substrate to form first and second gate electrodes with sloped sidewalls that angle toward each other and define a portion of the shape of sidewalls of a self-aligned contact window configured to hold a self-aligned contact pad therein.