Semiconductor package integral heat spreader

• US 20060170094A1
• Filed: 02/02/2005
• Published: 08/03/2006
• Est. Priority Date: 02/02/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Subramanian, Sankara J., Watwe, Abhay A.
• Application Number:
  US11/050,330
• Publication Number:
  US 20060170094A1
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3733 having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures H01L23/3732, H01L23/3737 take precedence
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

An integral heat spreader is disclosed wherein its physical characteristics are modified in regions between adjacent semiconductor devices. The modification improves the reliability of the semiconductor devices by reducing stiffness of the integral heat spreader.

Claims

1. An apparatus comprising:

a first semiconductor device and a second semiconductor device overlying a package substrate;

an integral heat spreader overlying the first semiconductor device and the second semiconductor device, wherein a physical property of the integral heat spreader is discontinuous in regions between the first semiconductor device and the second semiconductor device.

2. The apparatus of claim 1 wherein regions of the integral heat spreader between first semiconductor device and the second semiconductor device include a trench.

3. The apparatus of claim 2, wherein a ligament associated with the trench is discontinuous along the length of the trench.

4. The apparatus of claim 2, wherein the trench is further characterized as comprising a series of discrete trench segments that extend across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

5. The apparatus of claim 2, wherein the trench extends completely across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

6. The apparatus of claim 2, wherein the trench extends partially across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

7. The apparatus of claim 1, wherein regions between first semiconductor device and the second semiconductor device include an opening in the integral heat spreader.

8. The apparatus of claim 7, wherein the opening extends completely across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

9. The apparatus of claim 7, wherein the opening is further characterized as a plurality of discrete serial openings that extend completely across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

10. The apparatus of claim 7, wherein the opening partially extends across regions of the integral heat spreader between the first semiconductor device and the second semiconductor device.

11. A semiconductor package comprising:

At least a first and second semiconductor die; and

an integral heat spreader cooperatively coupled to the first and second semiconductor die, wherein the integral heat spreader includes a stiffness-reduction feature.

12. The semiconductor package of claim 11, wherein the stiffness-reduction feature is located between the first and second semiconductor die.

13. The semiconductor package of claim 11, wherein the stiffness-reduction feature is further characterized as an opening in the integral heat spreader between the first and second semiconductor die.

14. The semiconductor package of claim 13, wherein the opening extends completely across regions of the integral heat spreader between the first and second die.

15. The semiconductor package of claim 14, wherein the opening extends through an entire thickness of the integral heat spreader

16. The semiconductor package of claim 15, wherein the opening has a width dimension that approximates a dimension separating the first and second die.

17. The semiconductor package of claim 15, wherein the opening has a width dimension that is less than a dimension separating the first and second die.

18. The semiconductor package of claim 15, wherein the opening has a width dimension that is greater than a dimension separating the first and second die.

19. The semiconductor package of claim 13, wherein the opening extends partially across regions of the integral heat spreader between the first and second die.

20. The semiconductor package of claim 12, wherein the stiffness-reduction feature is further characterized as one of a plurality of discrete serial openings in the integral heat spreader between the first and second die and a plurality of discrete parallel openings in the integral heat spreader between the first and second die.

21. The semiconductor package of claim 20, wherein a length of the stiffness-reduction feature extends one of partially across regions of the integral heat spreader between the first and second die and completely across regions of the integral heat spreader between the first and second die.

22. The semiconductor package of claim 12, wherein the stiffness-reduction feature is further characterized as trench in portions of the integral heat spreader between the first and second die.

23. The semiconductor package of claim 22, wherein regions of the trench include discontinuities.

24. An integral heat spreader adapted to accommodate more than one semiconductor die, the integral heat spreader including a stress-reduction feature.

25. The integral heat spreader of claim 24, wherein the stress reduction feature is further characterized as one of a trench and an opening in the integral heat spreader.

26. The integral heat spreader of claim 25, wherein the stress reduction feature has a length that extends beyond a width of at least one of the more than one semiconductor die.

27. The integral heat spreader of claim 24, wherein the stress reduction feature is further characterized as one of an etched feature, a stamped feature, a raised feature, and a multi-layered feature between a first semiconductor die and a second semiconductor die.

28. The integral heat spreader of claim 24, wherein the integral heat spreader comprises multiple adjoining materials.

29. The integral heat spreader of claim 28, wherein the stress reduction feature comprises a material that reduces stiffness in regions of the integral heat spreader between semiconductor devices attached to the integral heat spreader.