Programmable devices to route signals on probe cards

• US 20060170435A1
• Filed: 01/31/2005
• Published: 08/03/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Henson, Roy J., Granicher, Dane C.
• Granted Patent: US 7,245,134 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC now with a known delay to connect to a device being tested.

Claims

1. A probe card assembly comprising a programmable IC to connect individual test channels to one of a plurality of test probes.

2. A probe card assembly of claim 1, wherein the programmable IC comprises a Field Programmable Gate Array (FPGA).

3. The probe card assembly of claim 1, wherein the FPGA does not include I/O buffering.

4. The probe card assembly of claim 1 further comprising a memory storing data for programming the programmable IC, wherein the data enables the programmable IC to be

first programmed to provide a connection from a test system controller through the programmable IC back to the test system controller to enable measurement of delay through the programmable IC, and

subsequently reprogrammed to connect to at least one device under test.

5. A probe card assembly of claim 1 further comprising:

a daughter card connected to a base PCB, the base PCB including connectors for connecting to a test system controller and routing lines from the connectors to the daughter card, the daughter card supporting the programmable IC.

6. The probe card assembly of claim 2, wherein a test program loaded into the FPGA is provided from a CAD design system used to develop the components on a wafer.

7. A test assembly including a probe card comprising:

a space transformer supporting test probes;

a base PCB comprising;

test head connectors for connecting to a test system controller;

a programmable IC;

channel lines provided from the test head connectors to the programmable IC; and

routing lines connecting the programmable IC to the test probes of the space transformer, wherein the programmable IC is programmable to selectively connect individual ones of the channel lines to different ones of the test probes.

8. The test assembly of claim 7 wherein the programmable IC comprises an FPGA.

9. The test assembly of claim 8, further comprising a memory storing data for programming the FPGA, wherein the data enables the FPGA to be

first programmed to provide a connection from the test system controller through the FPGA back to the test system controller to enable measurement of delay through the FPGA, and

subsequently reprogrammed to connect to the test system controller through the FPGA, the channel lines, the routing lines and the probes to at least one device under test.

10. The test assembly of claim 9 further comprising:

a test substrate having pads interconnected by traces, wherein the pads of the substrate are connectable to the test probes when the FPGA is first programmed to provide a connection from the test system controller through the FPGA back to the test system controller to enable measurement of delay through the FPGA.

11. The test assembly of claim 9 further comprising:

power lines provided from the test head connectors to the programmable IC, wherein the programmable IC is programmable to selectively connect individual ones of the power lines to different ones of the test probes.

12. A method for testing components on a wafer using a probe card, the method comprising:

programming a programmable IC on the probe card to selectively direct signals from a test system controller through the programmable IC on a test channel back to the test system controller;

measuring delay introduced in the test channel by the programmable IC; and

reprogramming the programmable IC to direct signals from the test system controller through the programmable IC on a test channel to connect to a device under test (DUT).

13. The method of claim 12 further comprising:

measuring delay through the channel to the DUT after the step of reprogramming the programmable IC with the delay introduced by the programmable IC cancelled out.

14. The method of claim 13, wherein prior to the steps of programming the programmable IC and reprogramming the programmable IC, the programmable IC is placed in a test environment for the step of measuring delay and allowed to come to substantially the same temperature as other components in the test environment.

15. The method of claim 14, wherein the step of programming is performed by loading a test program from a CAD design system used to develop components on the wafer.

16. The method of claim 14, wherein the step of programming is performed by a user interface connected to the probe card separate from an automatic test system connected to the probe card to provide test signals on the test channel.

17. The method of claim 14, further comprising the step of reconfiguring the IC, the IC comprising an FPGA, to redirect test signals to different ones of the plurality of test probes during testing of the components on the wafer.

18. The method of claim 16, wherein the FPGA is reconfigured in response to a change of pin functions of the components on the wafer.

19. A device comprising at least one of the components tested using the method of claim 14.

20. A processor readable medium storing code enabling programming of the IC according to the method of claim 14.