FRACTIONAL-N OFFSET PHASE LOCKED LOOP

• US 20060170505A1
• Filed: 01/31/2005
• Published: 08/03/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Humphreys, Scott Robert, Hietala, Alexander Wayne, Bunch, Ryan Lee, Hunt, Barry Travis Jr.
• Granted Patent: US 7,098,754 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03L 2207/12 Indirect frequency synthesis using a mixer in the phase-locked loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

Claims

1. A phase locked loop system comprising:

loop circuitry adapted to provide an output signal based on a divided reference signal;

combiner circuitry adapted to combine an initial fractional divide value and a modulation signal to provide a combined fractional divide value; and

a fractional-N divider adapted to fractionally divide a reference signal based on the combined fractional divide value to provide the divided reference signal such that the output signal is phase modulated.

2. The system of claim 1 wherein the loop circuitry adapted to provide the output signal comprises:

a phase detector adapted to compare a phase of the divided reference signal to a phase of a feedback signal;

a loop filter adapted to filter an output of the phase detector to provide a control signal;

controlled oscillator circuitry adapted to provide the output signal based on the control signal; and

feedback circuitry adapted to provide the feedback signal based on the output signal.

3. The system of claim 2 wherein the feedback circuitry comprises mixer circuitry adapted to multiply the output signal and a local oscillator signal to provide the feedback signal.

4. The system of claim 3 wherein the feedback circuitry further comprises filtering circuitry adapted to filter the feedback signal prior to providing the feedback signal to the phase detector.

5. The system of claim 4 further comprising a second phase locked loop adapted to provide the local oscillator signal based on a second reference signal.

6. The system of claim 5 wherein the local oscillator signal is also provided to the fractional-N divider as the reference signal

7. The system of claim 5 wherein the second phase locked loop is a fractional-N phase locked loop and provides the local oscillator signal based on the second reference signal and a second fractional divide value.

8. The system of claim 7 wherein the initial fractional divide value and the second fractional divide value are provided in concert such that the output signal is provided at a desired output frequency and spurs in the loop circuitry are avoided.

9. The system of claim 7 wherein the second fractional divide value is provided such that a desired output frequency of the output signal is an integer multiple of an intermediate frequency of the feedback signal and mixer output products output from the mixer circuitry appear at integer multiples of the intermediate frequency.

10. The system of claim 9 wherein the filtering circuitry comprises a low-pass filter adapted to filter the mixer output products output from the mixer circuitry to provide the feedback signal at the intermediate frequency.

11. The system of claim 9 wherein providing the second fractional divide value such that the desired output frequency of the output signal is the integer multiple of the intermediate frequency of the feedback signal ensures that fractional spurs appearing in the output signal are offset from the desired output frequency by at least an offset equal to the intermediate frequency.

12. The system of claim 11 wherein a loop response of the loop circuitry is such that the fractional spurs at frequencies other than the desired output frequency are filtered from the output signal.

16. The system of claim 1 wherein the combiner circuitry has a digital interface and the modulation signal is a digital signal.

17. The system of claim 16 wherein the phase locked loop system is part of modulation circuitry in a transmitter of a mobile terminal and the modulation circuitry provides an all digital path from processing circuitry of the mobile terminal to the digital interface of the combiner circuitry.

26. The system of claim 1 further comprising a digital pre-distortion filter adapted to pre-distort the modulation signal to provide a pre-distorted modulation signal to the combiner circuitry.

13. The system of 11 wherein the integer multiple is selected such that there is at least a minimum offset between fractional spurs appearing in the local oscillator signal and a frequency of the local oscillator signal.

14. The system of claim 13 wherein the second phase locked loop comprises a second loop filter adapted to filter the fractional spurs from the local oscillator signal.

15. The system of claim 13 wherein the minimum offset is defined based on a bandwidth of the second phase locked loop.

18. A method of providing a modulated signal using a phase locked loop system comprising:

providing an output signal based on a divided reference signal;

combining an initial fractional divide value and a modulation signal to provide a combined fractional divide value; and

fractionally dividing a reference signal based on the combined fractional divide value to provide the divided reference signal such that the output signal is phase modulated.

19. The method of claim 18 wherein providing the output signal comprises:

comparing a phase of the divided reference signal to a phase of a feedback signal to provide a comparison signal;

filtering the comparison signal to provide a control signal;

providing the control signal to a voltage controlled oscillator to control a frequency of the outputsignal; and

providing the feedback signal based on the output signal.

20. The method of claim 19 wherein providing the feedback signal comprises multiplying the output signal and a local oscillator signal to provide the feedback signal.

21. The method of claim 20 wherein providing the feedback signal further comprises filtering the feedback signal prior to providing the feedback signal to the phase detector.

22. The method of claim 20 further comprising providing the local oscillator signal based on a second reference signal.

23. The method of claim 22 further comprising providing the local oscillator signal to the fractional-N divider as the reference signal.

24. The method of claim 22 wherein providing the local oscillator signal comprises providing a fractional-N phase locked loop operating based on the second reference signal and a second fractional divide value.

25. The method of claim 24 further comprising providing the initial fractional divide value, and wherein providing the initial fractional divide value and providing the second fractional divide value comprise providing the initial fractional divide value and the second fractional divide value in concert such that the output signal is provided at a desired output frequency and spurs in the phase locked loop system are avoided.

27. The method of claim 18 further comprising pre-distorting the modulation signal such that the initial fractional divide value is combined with a pre-distorted version of the modulation signal to provide the combined fractional divide value.