DRIVING METHOD OF DISPLAY DEVICE

• US 20060170622A1
• Filed: 01/19/2006
• Published: 08/03/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd., Texas Instruments, Inc.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami
• Granted Patent: US 7,705,821 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A driving method of a display device for performing time-division gray scale display is disclosed, which is capable of inputting accurate data into a panel by using one memory. M groups each having a pair of a first period and a second period are provided in one frame period. Video signals are written into a memory in the first period of at least one group among the m groups, while video signals are read out from the memory in the respective second periods of the m groups. The start timing of reading out video signals from the memory is synchronized with the start timing of each of the n sub-frame periods.

Claims

1. A driving method of a display device comprising:

dividing one frame period into n (n is a natural number not less than

     2) sub-frame periods;

providing m (m is a natural number not less than n) groups each having a first period and a second period in the frame period;

writing a first video signal into a memory in a first period of at least one group among the m groups by using a controller; and

reading out a second video signal from the memory in a second period of the m groups by using the controller.

2. The driving method of a display device according to claim 1, wherein the number of read operations of the first video signal from the memory is larger than the number of write operations of the second video signal into the memory in the frame period.

3. The driving method of a display device according to claim 1,

wherein the memory has a first memory area and a second memory area,

wherein the first video signal is written into the first memory area while the second video signal stored in the second memory area is read out in an i-th (i is a natural number) frame period,

wherein a third video signal is written into the second memory area while the first video signal stored in the first memory area is read out in an (i+1)-th frame period that is right after the i-th frame period, and

wherein a fourth video signal is written into the first memory area while the third video signal stored in the second memory area is read out in an (i+2)-th frame period that is right after the (i+1)-th frame period.

4. The driving method of a display device according to claim 3,

wherein the first memory area has a memory capacity to store the first video signal corresponding to a plurality of pixels,

wherein the second memory area has a memory capacity to store the second video signal corresponding to the plurality of pixels, and

wherein the first video signal and the second video signal are video signals corresponding to different frame periods.

5. The driving method of a display device according to claim 1, wherein the second period is longer than the first period.

6. The driving method of a display device according to claim 1, wherein the memory is an SRAM.

7. The driving method of a display device according to claim 4, wherein each of the plurality of pixels has a light-emitting element.

8. The driving method of a display device according to claim 1, wherein the memory is a single-port memory.

9. The driving method of a display device according to claim 1, further comprising:

synchronizing start timing of reading out the second video signal from the memory with start timing of each of the n sub-frame periods.

10. The driving method of a display device according to claim 1, wherein the controller comprises a write-in memory, a readout memory, and a selector.

11. A driving method of a display device comprising:

dividing one frame period into n (n is a natural number not less than

     2) sub-frame periods;

providing m (m is a natural number not less than n) groups each having a first period and a second period in the frame period;

writing a first video signal into a memory in a first period of at least one group among the m groups by using a controller; and

reading out a second video signal from the memory in m second periods of the m groups by using the controller.

12. The driving method of a display device according to claim 11, wherein the number of read operations of the first video signal from the memory is larger than the number of write operations of the second video signal into the memory in the frame period.

13. The driving method of a display device according to claim 11,

wherein the memory has a first memory area and a second memory area,

wherein the first video signal is written into the first memory area while the second video signal stored in the second memory area is read out in an i-th (i is a natural number) frame period,

wherein a third video signal is written into the second memory area while the first video signal stored in the first memory area is read out in an (i+1)-th frame period that is right after the i-th frame period, and

wherein a fourth video signal is written into the first memory area while the third video signal stored in the second memory area is read out in an (i+2)-th frame period that is right after the (i+1)-th frame period.

14. The driving method of a display device according to claim 13,

wherein the first memory area has a memory capacity to store the first video signal corresponding to a plurality of pixels,

wherein the second memory area has a memory capacity to store the second video signal corresponding to the plurality of pixels, and

wherein the first video signal and the second video signal are video signals corresponding to different frame periods.

15. The driving method of a display device according to claim 11, wherein the second period is longer than the first period.

16. The driving method of a display device according to claim 11, wherein the memory is an SRAM.

17. The driving method of a display device according to claim 14, wherein each of the plurality of pixels has a light-emitting element.

18. The driving method of a display device according to claim 11, wherein the memory is a single-port memory.

19. The driving method of a display device according to claim 11, further comprising:

synchronizing start timing of reading out the second video signal from the memory with start timing of each of the n sub-frame periods.

20. The driving method of a display device according to claim 11, wherein the controller comprises a write-in memory, a readout memory, and a selector.

21. A driving method of a display device comprising:

dividing one frame period into n (n is a natural number not less than

     2) sub-frame periods;

providing m (m is a natural number not less than n) groups each having a first period and a second period in the frame period;

writing a first video signal into a memory in a first period of at least one group among the m groups through a bus; and

reading out a second video signal from the memory in a second period of the m groups through the bus.

22. The driving method of a display device according to claim 21, wherein the number of read operations of the first video signal from the memory is larger than the number of write operations of the second video signal into the memory in the frame period.

23. The driving method of a display device according to claim 21,

wherein the memory has a first memory area and a second memory area,

wherein the first video signal is written into the first memory area while the second video signal stored in the second memory area is read out in an i-th (i is a natural number) frame period,

wherein a third video signal is written into the second memory area while the first video signal stored in the first memory area is read out in an (i+1)-th frame period that is right after the i-th frame period, and

wherein a fourth video signal is written into the first memory area while the third video signal stored in the second memory area is read out in an (i+2)-th frame period that is right after the (i+1)-th frame period.

24. The driving method of a display device according to claim 23,

wherein the first memory area has a memory capacity to store the first video signal corresponding to a plurality of pixels,

wherein the second memory area has a memory capacity to store the second video signal corresponding to the plurality of pixels, and

wherein the first video signal and the second video signal are video signals corresponding to different frame periods.

25. The driving method of a display device according to claim 21, wherein the second period is longer than the first period.

26. The driving method of a display device according to claim 21, wherein the memory is an SRAM.

27. The driving method of a display device according to claim 24, wherein each of the plurality of pixels has a light-emitting element.

28. The driving method of a display device according to claim 21, wherein the memory is a single-port memory.

29. The driving method of a display device according to claim 21, further comprising:

synchronizing start timing of reading out the second video signal from the memory with start timing of each of the n sub-frame periods.

30. The driving method of a display device according to claim 21, wherein the bus connects the memory and a selector.