Low audible noise power supply method and controller therefor

• US 20060171179A1
• Filed: 02/17/2004
• Published: 08/03/2006
• Est. Priority Date: 02/17/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hall, Jefferson W., Basso, Christophe
• Granted Patent: US 7,583,522 B2
• Time in Patent Office: Days
• US Class Current: 363/95
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power controller forms drive pulses that reduces audible noise under light load conditions.

Claims

1. A method of forming a power system controller comprising:

coupling a PWM controller to receive an asymmetrical reference signal and responsively generate a set of drive pulses having widths suitable for forming a set of current pulses having an asymmetrical signal envelope.

2. The method of claim 1 further including coupling a control block to generate the asymmetrical reference signal responsively to a control signal representative of an output voltage increasing from a first value to a second value.

3. The method of claim 2 wherein coupling the control block to generate the asymmetrical reference signal includes coupling the control block to generate a triangular shaped reference signal.

4. The method of claim 3 wherein coupling the control block to generate the triangular shaped reference signal includes coupling the control block to generate the triangular shaped reference signal having a vertical cut-off.

5. The method of claim 1 wherein coupling the PWM controller to receive the asymmetrical reference signal includes coupling a comparator of the PWM controller to receive the asymmetrical reference signal.

6. The method of claim 1 wherein coupling the PWM controller to receive the asymmetrical reference signal and responsively generate the set of drive pulses includes coupling the PWM controller to receive the asymmetrical reference signal and responsively generate each drive pulse within the set with a width that is greater than a previous drive pulse within the set.

7. The method of claim 1 wherein coupling the PWM controller to receive the asymmetrical reference signal and responsively generate the set of drive pulses having widths suitable for forming the set of current pulses having the asymmetrical signal envelope includes coupling the PWM controller to responsively generate the set of drive pulses with each drive pulse having a width that is greater than an adjacent drive pulse.

8. The method of claim 1 wherein coupling the PWM controller to receive the asymmetrical reference signal includes coupling the PWM controller to receive an asymmetrical reference voltage.

16. The method of claim 1 wherein using the asymmetrical reference signal to control a width of the plurality of drive pulses includes using an asymmetrical reference voltage.

9. A method of operating a power supply comprising:

organizing output drive pulses of a power supply controller into a plurality of sets having a plurality of drive pulses wherein the plurality of sets are spaced apart in time; and

forming the plurality of drive pulses within at least one set to generate an asymmetrical signal envelope for a current.

10. The method of claim 9 wherein forming the plurality of drive pulses includes forming the plurality of drive pulses within the at least one set to have widths suitable to generate an asymmetrical signal envelope for the current through a transistor that receives the plurality of drive pulses.

11. The method of claim 9 wherein forming the plurality of drive pulses within the at least one set to generate the asymmetrical signal envelope includes forming the plurality of drive pulses to generate a triangle shaped signal envelope.

12. The method of claim 9 wherein forming the plurality of drive pulses within the at least one set to generate the asymmetrical signal envelope includes forming each drive pulse of the plurality of drive pulses to have a width that is greater than an adjacent drive pulse.

13. The method of claim 9 wherein organizing output drive pulses of the power supply controller into the plurality of sets includes spacing the plurality of sets apart in time by a time period of at lease one drive pulse.

14. The method of claim 9 wherein organizing output drive pulses of the power supply controller into the plurality of sets includes organizing the output drive pulses into the plurality of sets responsively to a control signal representative of an output voltage increasing from a first value to a second value.

15. The method of claim 9 wherein forming the plurality of drive pulses within the at least one set to generate the asymmetrical signal envelope includes using an asymmetrical reference signal to control a width of the plurality of drive pulses.

17. A power controller semiconductor device comprising:

a control block coupled to generate an asymmetrical reference signal; and

a PWM controller coupled to receive the asymmetrical reference signal and responsively generate a set of drive pulses having widths suitable to generate an asymmetrical signal envelope.

18. The power controller semiconductor device of claim 17 wherein the PWM controller coupled to receive the asymmetrical reference signal and responsively generate the set of drive pulses includes the PWM controller coupled to responsively generate the set of drive pulses having widths suitable to generate the asymmetrical signal envelope of a current through a transistor that receives the set of drive pulses.

19. The power controller semiconductor device of claim 17 wherein the control block coupled to generate the asymmetrical reference signal includes the control block coupled to generate the asymmetrical reference signal responsively to a control signal representative of an output voltage changing from a first value to a second value.

20. The power controller semiconductor device of claim 19 wherein the control block coupled to generate the asymmetrical reference signal includes the control block coupled to generate an asymmetrical reference voltage.