Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

• US 20060171203A1
• Filed: 03/15/2006
• Published: 08/03/2006
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Fu-Chang Hsu, Han-Rei Ma, Hsing-Ya Tsao, Peter W. Lee
• Inventors: Tsao, Hsing-Ya, Ma, Han-Rei, Lee, Peter W., Hsu, Fu-Chang
• Granted Patent: US 7,289,366 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Claims

1. A nonvolatile memory cell formed on a substrate comprising:

at least one floating gate storage transistor for storing a charge indicative of a memory state for said memory cell, each floating gate storage transistor comprising;

a drain region,

a source region,

a floating gate placed over a channel region of said floating gate transistor and between said source region and said drain region of said floating gate transistor for storing said charge; and

a gating transistor having a source connected to the drain region of one of said floating gate transistors, a drain connected to a bit line of an array incorporating a plurality of said nonvolatile memory cells, and a gate connected to a select gate signal to selectively apply a bit line voltage signal from said bit line to the drain region of said one floating gate transistors;

wherein said floating gate transistor has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.

2. The nonvolatile memory cell of claim 1 wherein said coupling ratio is less than 50%.

3. The nonvolatile memory cell of claim 1 wherein said nonvolatile memory cell is in communication with a programming apparatus that places a charge upon said floating gate, said programming apparatus comprising:

means for applying a moderately high positive voltage to said control gate of said floating gate transistor;

means for applying an intermediate positive voltage to said drain region of said floating gate transistor;

means for setting said select gate signal and thus said gate of said gating transistor to a very large positive voltage; and

means for applying a ground reference voltage to said source region of said floating gate transistor.

4. The nonvolatile memory cell of claim 3 wherein said nonvolatile memory cell comprises one floating gate storage transistor in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NOR nonvolatile memory array.

5. The nonvolatile memory cell of claim 3 wherein said nonvolatile memory cell comprises a plurality of serially connected floating gate storage transistors in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NAND nonvolatile memory array.

6. The nonvolatile memory cell of claim 3 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

7. The nonvolatile memory cell of claim 3 wherein said intermediate positive voltage is approximately 5.0V

8. The nonvolatile memory cell of claim 3 wherein said very large positive voltage is from approximately +15V to approximately +22V.

9. The nonvolatile memory cell of claim 3 wherein said means for applying said moderately high positive voltage, said means for applying said intermediate positive voltage, and said means for applying said ground reference voltage applies said moderately high positive voltage, said intermediate positive voltage, and said ground reference voltage for a duration of from approximately 1 μ

s to approximately 100 μ

s.

10. The nonvolatile memory cell of claim 1 wherein said memory cell is in communication with an erasing apparatus to remove electrical charge from said floating gate, said erasing apparatus comprising:

means for applying a very high negative voltage to said control gate; and

means for applying a ground reference voltage to said select gate.

11. The nonvolatile memory cell of claim 10 wherein said very large negative voltage is from approximately −

15V to approximately −

22V.

12. The nonvolatile memory cell of claim 10 wherein said erasing apparatus further comprises:

means for disconnecting the source region and the drain region to allow said source region and said drain region to float.

13. The nonvolatile memory cell of claim 10 wherein said erasing apparatus further comprises:

means for applying a ground reference voltage to said source region and said drain region.

14. The nonvolatile memory cell of claim 10 wherein said erasing apparatus has a duration of from approximately 1 ms to approximately 1 s.

15. A nonvolatile memory array formed on a substrate comprising:

a plurality nonvolatile memory cells arranged in rows and columns comprising;

at least one floating gate storage transistor for storing a charge indicative of a memory state for said memory cell, each floating gate storage transistor comprising;

a drain region,

a source region,

a floating gate placed over a channel region of said floating gate transistor and between said source region and said drain region of said floating gate transistor for storing said charge; and

a gating transistor having a source connected to the drain region of one of said floating gate transistors, a drain connected to a bit line of an array incorporating a plurality of said nonvolatile memory cells, and a gate connected to a select gate signal to selectively apply a bit line voltage signal from said bit line to the drain region of said one floating gate transistors;

wherein said floating gate transistor has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.

16. The nonvolatile memory array of claim 15 wherein said coupling ratio is less than 50%.

17. The nonvolatile memory array of claim 15 wherein said nonvolatile memory array is in communication with a programming apparatus that places a charge upon said floating gate, said programming apparatus comprising:

means for applying a moderately high positive voltage to said control gate of said floating gate transistor;

means for applying an intermediate positive voltage to said drain region of said floating gate transistor;

means for setting said select gate signal and thus said gate of said gating transistor to a very large positive voltage; and

means for applying a ground reference voltage to said source region of said floating gate transistor.

18. The nonvolatile memory array of claim 17 wherein said nonvolatile memory array comprises one floating gate storage transistor in series with said gating transistor and an array of said nonvolatile memory arrays includes a plurality of said nonvolatile memory arrays configured as a NOR nonvolatile memory array.

19. The nonvolatile memory array of claim 17 wherein said nonvolatile memory array comprises a plurality of serially connected floating gate storage transistors in series with said gating transistor and an array of said nonvolatile memory arrays includes a plurality of said nonvolatile memory arrays configured as a NAND nonvolatile memory array.

20. The nonvolatile memory array of claim 17 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

21. The nonvolatile memory array of claim 17 wherein said intermediate positive voltage is approximately 5.0V

22. The nonvolatile memory array of claim 17 wherein said very large positive voltage is from approximately +15V to approximately +22V.

23. The nonvolatile memory array of claim 17 wherein said means for applying said moderately high positive voltage, said means for applying said intermediate positive voltage, and said means for applying said ground reference voltage applies said moderately high positive voltage, said intermediate positive voltage, and said ground reference voltage for a duration of from approximately 1 μ

s to approximately 100 μ

s.

24. The nonvolatile memory array of claim 15 wherein said memory cell is in communication with an erasing apparatus to remove electrical charge from said floating gate, said erasing apparatus comprising:

means for applying a very high negative voltage to said control gate; and

means for applying a ground reference voltage to said select gate.

25. The nonvolatile memory cell of claim 24 wherein said very large negative voltage is from approximately −

15V to approximately −

22V.

26. The nonvolatile memory array of claim 24 wherein said erasing apparatus further comprises:

means for disconnecting the source region and the drain region to allow said source region and said drain region to float.

27. The nonvolatile memory array of claim 24 wherein said erasing apparatus further comprises:

means for applying a ground reference voltage to said source region and said drain region.

28. The nonvolatile memory array of claim 24 wherein said erasing apparatus has a duration of from approximately 1 ms to approximately 1 s.

29. A method for operating a nonvolatile memory cell formed on a substrate comprising the steps of:

forming at least one floating gate storage transistor for storing a charge indicative of a memory state for said memory cell on said substrate, each floating gate storage transistor formed by the steps of;

forming a drain region,

forming a source region, and

placing a floating gate over a channel region of said floating gate transistor and between said source region and said drain region of said floating gate transistor for storing said charge; and

forming a gating transistor having a source connected to the drain region of one of said floating gate transistors, a drain connected to a bit line of an array incorporating a plurality of said nonvolatile memory cells, and

a gate connected to a select gate signal to selectively apply a bit line voltage signal from said bit line to the drain region of said one floating gate transistors;

wherein said floating gate transistor has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.

30. The method for operating a nonvolatile memory cell of claim 29 wherein said coupling ratio is less than 50%.

31. The method for operating a nonvolatile memory cell of claim 29 further comprises programming said nonvolatile memory cell by placing a charge upon said floating gate, said programming said nonvolatile memory cell comprises the steps of:

applying a moderately high positive voltage to said control gate of said floating gate transistor;

applying an intermediate positive voltage to said drain region of said floating gate transistor;

setting said select gate signal and thus said gate of said gating transistor to a very large positive voltage; and

applying a ground reference voltage to said source region of said floating gate transistor.

32. The method for operating a nonvolatile memory cell of claim 31 wherein said method for operating a nonvolatile memory cell comprises the step of forming one floating gate storage transistor in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NOR nonvolatile memory array.

33. The method for operating a nonvolatile memory cell of claim 31 wherein said method for operating a nonvolatile memory cell comprises the step of forming a plurality of serially connected floating gate storage transistors in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NAND nonvolatile memory array.

34. The method for operating a nonvolatile memory cell of claim 31 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

35. The method for operating a nonvolatile memory cell of claim 31 wherein said intermediate positive voltage is approximately 5.0V

36. The method for operating a nonvolatile memory cell of claim 31 wherein said very large positive voltage is from approximately +15V to approximately +22V.

37. The method for operating a nonvolatile memory cell of claim 31 wherein said applying said moderately high positive voltage, said applying said intermediate positive voltage, and said applying said ground reference voltage have a duration of from approximately 1 μ

s to approximately 100 μ

s.

38. The method for operating a nonvolatile memory cell of claim 29 further comprises the step of erasing said memory cell to remove electrical charge from said floating gate, said erasing comprising the steps of:

applying a very high negative voltage to said control gate; and

applying a ground reference voltage to said select gate.

39. The method for operating a nonvolatile memory cell of claim 38 wherein said very large negative voltage is from approximately −

15V to approximately −

22V.

40. The method for operating a nonvolatile memory cell of claim 38 wherein said erasing further comprises the step of:

disconnecting the source region and the drain region to allow said source region and said drain region to float.

41. The method for operating a nonvolatile memory cell of claim 38 wherein said erasing further comprises the step of:

applying a ground reference voltage to said source region and said drain region.

42. The method for operating a nonvolatile memory cell of claim 38 wherein said erasing has a duration of from approximately 1 ms to approximately 1 s.

43. An apparatus for operating a nonvolatile memory cell formed on a substrate comprising the steps of:

means for forming at least one floating gate storage transistor for storing a charge indicative of a memory state for said memory cell on said substrate, each means for forming said floating gate storage transistor comprises;

means for forming a drain region,

means for forming a source region, and

means for placing a floating gate over a channel region of said floating gate transistor and between said source region and said drain region of said floating gate transistor for storing said charge; and

means for forming a gating transistor having a source connected to the drain region of one of said floating gate transistors, a drain connected to a bit line of an array incorporating a plurality of said nonvolatile memory cells, and a gate connected to a select gate signal to selectively apply a bit line voltage signal from said bit line to the drain region of said one floating gate transistors;

wherein said floating gate transistor has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.

44. The apparatus for operating a nonvolatile memory cell of claim 43 wherein said coupling ratio is less than 50%.

45. The apparatus for operating a nonvolatile memory cell of claim 43 further comprises means for programming said nonvolatile memory cell by placing a charge upon said floating gate, said means for programming said nonvolatile memory cell comprises:

means for applying a moderately high positive voltage to said control gate of said floating gate transistor;

means for applying an intermediate positive voltage to said drain region of said floating gate transistor;

means for setting said select gate signal and thus said gate of said gating transistor to a very large positive voltage; and

means for applying a ground reference voltage to said source region of said floating gate transistor.

46. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said apparatus for operating a nonvolatile memory cell comprises means for forming one floating gate storage transistor in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NOR nonvolatile memory array.

47. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said apparatus for operating a nonvolatile memory cell comprises means for forming a plurality of serially connected floating gate storage transistors in series with said gating transistor and an array of said nonvolatile memory cells includes a plurality of said nonvolatile memory cells configured as a NAND nonvolatile memory array.

48. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

49. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said intermediate positive voltage is approximately 5.0V

50. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said very large positive voltage is from approximately +15V to approximately +22V.

51. The apparatus for operating a nonvolatile memory cell of claim 45 wherein said means for applying said moderately high positive voltage, said means for applying said intermediate positive voltage, and said means for applying said ground reference voltage have a duration of from approximately 1 μ

s to approximately 100 μ

s.

52. The apparatus for operating a nonvolatile memory cell of claim 43 further comprises means for erasing said memory cell to remove electrical charge from said floating gate, said means for erasing comprising:

means for applying a very high negative voltage to said control gate; and

means for applying a ground reference voltage to said select gate.

53. The apparatus for operating a nonvolatile memory cell of claim 52 wherein said very large negative voltage is from approximately −

15V to approximately −

22V.

54. The apparatus for operating a nonvolatile memory cell of claim 52 wherein said means for erasing further comprises:

means for disconnecting the source region and the drain region to allow said source region and said drain region to float.

55. The apparatus for operating a nonvolatile memory cell of claim 52 wherein said means for erasing further comprises:

means for applying a ground reference voltage to said source region and said drain region.

56. The apparatus for operating a nonvolatile memory cell of claim 52 wherein said means for erasing has a duration of from approximately 1 ms to approximately 1 s.