Method for analyzing critical defects in analog integrated circuits

• US 20060171221A1
• Filed: 01/31/2005
• Published: 08/03/2006
• Est. Priority Date: 01/31/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Phan, Tony T., Mollat, Martin B., Khandekar, Milind V., Flessner, Kyle M.
• Granted Patent: US 7,415,378 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.

Claims

1. A method for analyzing critical defects in analog integrated circuits, comprising;

fault testing a power field effect transistor portion of an analog integrated circuit to obtain electrical failure data;

performing an in-line optical inspection of the analog integrated circuit to obtain physical defect data;

correlating the electrical failure data and physical defect data to analyze critical defects.

2. The method as recited in claim 1 wherein the power field effect transistor portion is a lateral drain metal oxide semiconductor (LDMOS) transistor.

3. The method as recited in claim 1 wherein the power field effect transistor portion is a drain extended metal oxide semiconductor (DE-MOS) transistor.

4. The method as recited in claim 1 wherein correlating the electrical failure data and physical defect data includes producing an overlay of the electrical failure data and the physical defect data.

5. The method as recited in claim 4 wherein the overlay is visual.

6. The method as recited in claim 4 wherein coordinates of the electrical failure data is mapped in relation to the analog integrated circuit and the coordinates of the physical defect data is mapped in relation to the associated integrated circuit, and wherein the coordinates of each are used to overlay the electrical failure data and physical defect data

7. The method as recited in claim 1 further including inputting the electrical failure data and physical defect data into a overlay analysis tool then correlating the electrical failure data and physical defect data using the overlay analysis tool.

8. The method as recited in claim 7 wherein the overlay analysis tool includes software on a computer.

9. The method as recited in claim 1 wherein fault testing includes probe testing to determine whether the power field effect transistor passes or fails.

10. The method as recited in claim 1 wherein performing an in-line optical inspection includes performing an in-line optical inspection using a KLA or AIT in-line optical inspection tool.

11. The method as recited in claim 1 wherein the fault testing and performing are conducted on a wafer including a plurality of dies each having integrated circuits.

12. The method as recited in claim 11 wherein the wafer is a production wafer and not a test wafer.

13. The method as recited in claim 1 further including linking each analyzed critical defects to a particular production process or series of production processes.

14. The method as recited in claim 13 further including tabulating the number of analyzed critical defects linked to each particular process step or series of steps.

15. The method as recited in claim 14 further including optimizing one or more particular process steps or series of steps in order of importance based upon the tabulated number of analyzed critical defects linked to each particular process step or series of steps.

16. A system for analyzing critical defects in analog integrated circuits, comprising;

a fault testing subsystem configured to test a power field effect transistor portion of an analog integrated circuit to obtain electrical failure data;

an optical inspection subsystem configured to perform an in-line optical inspection of the analog integrated circuit to obtain physical defect data;

a correlation subsystem configured to correlate the electrical failure data and physical defect data to analyze critical defects.

17. The system as recited in claim 16 wherein the correlation subsystem resides on a computer subsystem.

18. The system as recited in claim 16 wherein the correlation subsystem resides within the fault testing subsystem or the optical inspection subsystem.

19. The system as recited in claim 16 wherein the power field effect transistor portion is a lateral drain metal oxide semiconductor (LDMOS) transistor and the fault testing subsystem is configured to test the lateral drain metal oxide semiconductor (LDMOS) transistor.

20. The system as recited in claim 16 wherein the fault testing subsystem includes a probe tester.