CHIP LAYOUT FOR MULTIPLE CPU CORE MICROPROCESSOR

• US 20060171244A1
• Filed: 02/03/2005
• Published: 08/03/2006
• Est. Priority Date: 02/03/2005
• Status: Abandoned Application

• Current Assignee: Yoshiyuki Ando
• Original Assignee: Yoshiyuki Ando
• Inventors: Ando, Yoshiyuki
• Application Number:
  US10/906,108
• Publication Number:
  US 20060171244A1
• Time in Patent Office: Days
• US Class Current: 365/52
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor chip on a semiconducting substrate has at least two CPU cores that have hot spots on one side, a private cache memory for each CPU core that is located on the same side of said CPU core as the hot spot, a common cache memory that can be accessed by each CPU core, and an on-chip bus line connecting the CPU cores to the common cache memory. The CPU cores are located on each side of the on-chip bus line with their hot spots and their private cache memories positioned away from the on-chip bus line. Some of the CPU cores on the chip may be low power consumption CPU core and some of the CPU cores may be high speed CPU cores. The CPU cores may also be the same or different performance or purpose cores. A clock generator circuit may connect the CPU cores.

Claims

1. A microprocessor chip on a semiconducting substrate comprising

(A) at least two CPU cores that have a hot spot on one side;

(B) a private cache memory for each CPU core, where said private cache memories are located on the same side of said CPU core as said hot spots;

(C) a common cache memory that can be accessed by each CPU core; and

(D) an on-chip bus line connecting said CPU cores to said common cache memory, where CPU cores are located on each side of said on-chip bus line with their hot spots and their private cache memories positioned away from said on-chip bus line.

2. A microprocessor chip according to claim 1 wherein there are two CPU cores on said chip.

3. A microprocessor chip according to claim 1 wherein at least one of said CPU cores on said chip is a low power consumption CPU core and at least one of said CPU core on said chip is a high speed CPU core.

4. A microprocessor chip according to claim 3 wherein said high speed CPU cores are located closer to said on-chip bus line than said low power consumption CPU cores.

5. A microprocessor chip according to claim 3 wherein said high speed CPU cores are located closer to said common cache memory than said low power consumption CPU cores.

6. A microprocessor chip according to claim 3 wherein the execution of programs can be assigned to either said high speed CPU cores or to said low power consumption CPU cores.

7. A microprocessor chip according to claim 1 wherein at least two of said CPU cores on said chip are the same.

8. A microprocessor chip according to claim 1 wherein at least one of said CPU cores on said chip is different from another CPU core on said chip in its operating power requirements and processing capabilities.

9. A microprocessor chip according to claim 1 wherein at least two of said CPU cores differ in their private cache size.

10. A microprocessor chip according to claim 1 wherein all of said CPU cores on said chip differ in their respective operating power requirements and processing capabilities.

11. A microprocessor chip according to claim 1 wherein there are three CPU cores on said chip.

12. A microprocessor chip according to claim 1 wherein there are four CPU cores on said chip.

13. A microprocessor chip according to claim 1 wherein a clock generator circuit connects said CPU cores.

14. A microprocessor chip according to claim 1 wherein said hot spots are located at said private cache memories.

15. A microprocessor chip according to claim 1 wherein CPU cores that are farther from said common cache memory have a larger private cache size.

16. A method of processing data using a microprocessor chip according to claim 1 comprising executing a program using at least one of said CPU cores.

18. A microprocessor chip according to claim 16 wherein at least one of said CPU cores on said chip is different from another CPU core on said chip in its operating power requirements and processing capabilities.

20. A microprocessor chip according to claim 18 wherein there are four CPU core, two on each side of said on-chip bus line.

17. A microprocessor chip on a semiconducting substrate comprising

(A) at least four CPU cores, where said CPU cores have a hot spot that is located on one side;

(B) a private cache memory for each CPU core that is located on the same side of said CPU core as said hot spot;

(C) a common cache memory that can be accessed by each CPU core; and

(D) an on-chip bus line that connects said CPU cores to said common cache memory, where CPU cores are located on each side of said on-chip bus line with their hot spots and their private cache memories positioned away from said on-chip bus line.

19. A microprocessor chip on a semiconducting substrate comprising

(A) at least four CPU cores, where said CPU cores have a hot spot that is located on one side, and at least one of said CPU cores on said chip is a low power consumption core and at least one of said CPU cores on said chip is a high speed core;

(B) a clock generator circuit connecting said CPU cores;

(C) a private cache memory for each CPU core that is located on the same side of said CPU core as said hot spot;

(C) a common cache memory that can be accessed by each CPU core; and

(E) an on-chip bus line connecting said CPU cores to said common cache memory, where CPU cores are located on each side of said on chip bus line with their hot spots and their private cache memories positioned away from said on-chip bus line and said at least one high speed CPU core is located closer to said on-chip bus line than said at least one low power consumption CPU core.