Inspection apparatus for inspecting patterns of a substrate

• US 20060171593A1
• Filed: 02/01/2006
• Published: 08/03/2006
• Est. Priority Date: 02/01/2005
• Status: Abandoned Application

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Fujii, Dai, Nakano, Michio, Miyai, Hiroshi, Fujisawa, Takako, Hayakawa, Koichi, Nojiri, Masaaki
• Application Number:
  US11/344,101
• Publication Number:
  US 20060171593A1
• Time in Patent Office: Days
• US Class Current: 382/209
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Claims

1. A pattern inspection apparatus comprising:

irradiating means for irradiating light, a laser beam, or a charged particle beam onto a substrate on which patterns have been formed;

detecting means for detecting a signal which is generated from said substrate by said irradiation;

image data storing means for forming an image from the signal detected by said detecting means and storing image data;

comparing condition designating means for designating information of an inspection area on said substrate and information of a comparing period in association with each other;

comparing means for comparing the image data stored in said image data storing means with another image data corresponding to the comparing period designated for the inspection area to which the image data belongs in accordance with the information of the inspection area and the information of the comparing period designated by said comparing condition designating means; and

discriminating means for discriminating a defect on the patterns from a comparison result of said comparing means.

2. An apparatus according to claim 1, wherein said comparing condition designating means designates the inspection area by start coordinates and end coordinates and designates said comparing period every inspection area.

3. An apparatus according to claim 1, wherein when a plurality of inspection areas of different comparing periods are designated by said comparing condition designating means, said comparing means compares the image data of each inspection area with another image data corresponding to the comparing period designated for each of the inspection areas.

4. An apparatus according to claim 3, wherein different comparing periods are designated for a plurality of inspection areas on a same stripe.

5. An apparatus according to claim 1, wherein when a plurality of comparing periods are designated for one inspection area by said comparing condition designating means, said comparing means compares the image data of said inspection area with a plurality of image data corresponding to said plurality of comparing periods.

6. An apparatus according to claim 1, wherein said irradiating means scans and irradiates an electron beam in one-dimensional direction and has a stage for moving said substrate in the direction which crosses said electron beam scanning direction, and said image data is one-dimensional image data.

7. A pattern inspection apparatus comprising:

an image memory for storing image data obtained by photographing a semiconductor wafer; and

a memory controller for extracting an inspection image and a reference image for comparison from said image memory and transferring them to an image processing unit,

wherein said memory controller receives a head address of a defective image in said image memory and reference image information showing a relative position of the reference image for said defective image, extracts said inspection image from said image memory by using said received head address of the defective image, and extracts said reference image from said image memory by using said received head address of the defective image and the reference image information.

8. An apparatus according to claim 7, wherein said reference image information is relative position information of a chip in a die comparison.

9. An apparatus according to claim 7, wherein said reference image information is a cell pitch in a cell comparison.

10. A pattern inspection apparatus comprising:

an image memory for storing image data obtained by photographing a semiconductor wafer on which a plurality of chips have been formed;

a memory controller for extracting an inspection image and a reference image for comparison from said image memory and transferring them to an image processing unit; and

a whole control unit for holding information regarding an obtaining method of the reference image in each area in said chip, forming reference image information showing the obtaining method of the reference image for a defective image on the basis of a position of a detected defect in said chip, and outputting a head address of the defective image in said image memory and said reference image information to said memory controller,

wherein said memory controller extracts said inspection image from said image memory by using the head address of said defective image received from said whole control unit and extracts said reference image from said image memory by using the head address of said defective image and the reference image information.

11. An apparatus according to claim 10, wherein said reference image information includes identification information to identify a cell comparison or a die comparison, a cell pitch in the case of the cell comparison, and relative position information of the chip in the case of the die comparison.

12. An apparatus according to claim 10, wherein said memory controller holds a memory table in which the head address of the defective image and the corresponding reference image information have been recorded for each defect.

13. A pattern inspection apparatus comprising:

irradiating means for irradiating light, a laser beam, or a charged particle beam onto a substrate on which patterns have been formed;

detecting means for detecting a signal which is generated from said substrate by said irradiation;

image data storing means for forming an image from the signal detected by said detecting means and storing image data;

inspecting condition setting means for setting information of an inspection area on said substrate and information of an inspection threshold value as a defect discriminating condition in association with each other;

comparing means for comparing the image data stored in said image data storing means with another corresponding image data in accordance with the information of the inspection area and the information of the inspection threshold value set by said inspecting condition setting means; and

discriminating means for discriminating a defect on the patterns from a comparison result of said comparing means.

14. An apparatus according to claim 13, wherein said inspecting condition setting means also sets a comparing period in association with the information of said inspection area.

15. An apparatus according to claim 13, wherein a plurality of inspection areas on a same stripe are inspected by a plurality of inspection threshold values.

16. An apparatus according to claim 13, wherein said inspecting condition setting means sets a plurality of inspection threshold values in dependence on a position on the substrate.

17. An apparatus according to claim 13, wherein said inspecting condition setting means designates the inspection area by start coordinates and end coordinates.