Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor

• US 20060172556A1
• Filed: 02/01/2006
• Published: 08/03/2006
• Est. Priority Date: 02/01/2005
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bather, Wayne A., Mehta, Narendra S., Yocum, Troy
• Application Number:
  US11/344,998
• Publication Number:
  US 20060172556A1
• Time in Patent Office: Days
• US Class Current: 438/794
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3125 layers comprising silazane compounds
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure (230) over a substrate (210), and forming a strain inducing film (330, 520, 530 or 810) over the substrate (210) and proximate the gate structure (230), the strain inducing film (330, 520, 530 or 810) comprising a bis t-butylaminosilane (BTBAS) silicon nitride layer formed using ratio of bis t-butylaminosilane (BTBAS) to ammonia (NH₃) of 1:1 or greater.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a gate structure over a substrate; and

forming a strain inducing film over the substrate and proximate the gate structure, the strain inducing film-comprising a bis t-butylaminosilane (BTBAS) silicon nitride layer formed using ratio of bis t-butylaminosilane (BTBAS) to ammonia (NH₃) of 1;

1 or greater.

2. The method as recited in claim 1 wherein forming the strain inducing film includes forming the strain inducing film using a temperature of less than about 600°

C.

3. The method as recited in claim 1 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a peak carbon concentration of about 1.1E21 atoms/cm³ or greater.

4. The method as recited in claim 3 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a peak carbon concentration of about 2.0E21 atoms/cm³ or greater.

5. The method as recited in claim 1 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a stress value of about 1.25 GPa or greater.

6. The method as recited in claim 1 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a stress value of about 2.25 GPa or greater.

7. The method as recited in claim 1 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer is located proximate a sidewall of the gate structure.

8. The method as recited in claim 7 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer forms at least a portion of a sidewall spacer or offset spacer.

9. The method as recited in claim 1 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer is formed as a capping layer over the substrate and gate structure.

10. The method as recited in claim 1 further including forming a dielectric layer having one or more interconnects therein over the gate structure, the one or more interconnects contacting the gate structure to form an operational integrated circuit.

11. A semiconductor device, comprising:

a gate structure located over a substrate;

a strain inducing film located over the substrate and proximate the gate structure, the strain inducing film comprising a bis t-butylaminosilane (BTBAS) silicon nitride layer having a peak carbon concentration of about 1.1E21 atoms/cm³ or greater.

12. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a peak carbon concentration of about 1.5E21 atoms/cm³ or greater

13. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a peak carbon concentration of about 2.0E21 atoms/cm³ or greater.

14. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a stress value of about 1.25 GPa or greater.

15. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a stress value of about 1.75 GPa or greater.

16. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer has a stress value of about 2.25 GPa or greater.

17. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer is located proximate a sidewall of the gate structure.

18. The semiconductor device as recited in claim 17 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer forms at least a portion of a sidewall spacer or offset spacer.

19. The semiconductor device as recited in claim 11 wherein the bis t-butylaminosilane (BTBAS) silicon nitride layer is formed as a capping layer over the substrate and gate structure.

20. The semiconductor device as recited in claim 11 further including a dielectric layer having one or more interconnects therein located over the gate structure, the one or more interconnects contacting the gate structure and forming an operational integrated circuit.