Method and apparatus for encoding and decoding data using a pseudo-random interleaver

• US 20060174184A1
• Filed: 02/01/2005
• Published: 08/03/2006
• Est. Priority Date: 02/01/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Song, Hongwei, Keirn, Zachary, Stroud, Peter, Ashley, Jonathan
• Granted Patent: US 7,526,707 B2
• Time in Patent Office: Days
• US Class Current: 714/800
• CPC Class Codes: G11B 20/1866 by interleaving G11B20/1809 takes precedence
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A pseudo-random bit interleaver and de-interleaver comprising a source for generating pseudo-random numbers and transformation logic that transforms each pseudo-random number generated by the source into a plurality of different pseudo-random numbers. Each of the transformed pseudo-random numbers identifying a parity equation to which an incoming bit will be assigned for computing parity.

Claims

1. A pseudo-random bit interleaver or de-interleaver that receives incoming bits comprising:

a source for generating pseudo-random numbers (PRNs) made up of bits; and

transformation logic configured to transform each PRN generated by the source into a plurality of different PRNs, each of said plurality of PRNs identifying a parity equation to which a respective one of the incoming bits will be assigned.

2. The pseudo-random bit interleaver or de-interleaver of claim 1, wherein the source comprises a linear feedback shift register.

3. The pseudo-random bit interleaver or de-interleaver of claim 1, wherein the source comprises a state machine.

4. The pseudo-random bit interleaver or de-interleaver of claim 1, wherein the source comprises a memory device.

5. The pseudo-random bit interleaver or de-interleaver of claim 1, wherein the interleaver is formed in an integrated circuit (IC).

6. The pseudo-random bit interleaver or de-interleaver of claim 5, wherein the transformation logic comprises wires formed in the IC that reorder the bits of the PRN generated by the source.

7. The pseudo-random bit interleaver or de-interleaver of claim 5, wherein the transformation logic comprises matrix multiplication logic configured to multiply each PRN generated by the source by a plurality of different nonsingular binary matrices.

8. The pseudo-random bit interleaver or de-interleaver of claim 1, further comprising:

parity equation logic configured to compute parity of each parity equation by exclusive ORing incoming bits together that have been assigned to a same parity equation.

9. A method for pseudo-randomly interleaving or de-interleaving incoming bits comprising:

generating pseudo-random numbers with a pseudo-random number generation source; and

transforming each pseudo-random number generated by the source into a plurality of different pseudo-random numbers, each of said plurality of pseudo-random numbers identifying a parity equation to which a respective one of the incoming bits will be assigned.

10. The method of claim 9, wherein the source comprises a linear feedback shift register.

11. The method of claim 9, wherein the source comprises a state machine.

12. The method of claim 9, wherein the source comprises a memory device.

13. The method of claim 9, wherein the interleaver is formed in an integrated circuit (IC).

14. The method of claim 13, wherein each pseudo-random number comprises a sequence of bits, and wherein the transformation is performed by wires formed in the IC that reorder the bit sequences generated by the source into a plurality of different bit sequences.

15. The method of claim 13, wherein each pseudo-random number comprises a sequence of bits, and wherein the transformation is performed by matrix multiplication logic formed in the IC that multiplies each bit sequence generated by the source by a plurality of different nonsingular binary matrices to transform each bit sequence generated by the source into a plurality of different bit sequences.

16. The method of claim 9, further comprising computing parity of each parity equation by exclusive ORing incoming bits together that have been assigned to a same parity equation.