Electrostatic discharge circuit and method of dissipating an electrostatic current

• US 20060175663A1
• Filed: 08/11/2005
• Published: 08/10/2006
• Est. Priority Date: 02/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Chan-hee, Kim, Han-gu, Jang, Sung-pil
• Granted Patent: US 7,888,739 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.

Claims

1. An electrostatic discharge circuit comprising:

a first well of a first conductivity type, connected to a first pad;

a second well of the first conductivity type, connected to a second pad;

a third well of a second conductivity type, connected to a first pad; and

a switching pathway of the first conductivity type, formed in the third well, and connecting the first well and the second well.

2. The electrostatic discharge circuit of claim 1, wherein the first conductivity type is positive and the second conductivity type is negative.

3. The electrostatic discharge circuit of claim 1, wherein the first pad is connected to a drive voltage and the second pad is connected to a ground voltage.

4. The electrostatic discharge circuit of claim 1, wherein the switching pathway forms a resistor path to discharge an electrostatic current.

5. The electrostatic discharge circuit of claim 4, wherein the first well, the second well, and the third well form a bipolar transistor path to discharge the electrostatic current.

6. The electrostatic discharge circuit of claim 5, wherein the resistor path and the bipolar transistor path alternately discharge the electrostatic current.

7. The electrostatic discharge circuit of claim 1, wherein the first well includes a third diffusion layer of the first conductivity type, the third diffusion layer connected to the first pad.

8. The electrostatic discharge circuit of claim 7, wherein the second well includes a second diffusion layer of the second conductivity type and a fourth diffusion layer of the first conductivity type, the second diffusion layer and the fourth diffusion layer connected to the second pad.

9. The electrostatic discharge circuit of claim 8, wherein the third well includes a first diffusion layer of the second conductivity type, the first diffusion layer connected to the first pad.

10. The electrostatic discharge circuit of claim 1, wherein at least one of the first well and the second well are formed in the third well.

11. The electrostatic discharge circuit of claim 10, wherein the first well is formed in the third well and the second well is formed in a substrate of the first conductivity type.

12. The electrostatic discharge circuit of claim 1, further comprising:

an isolation layer defining an active region including the switching pathway and a guard ring of the second conductivity type, for defining a lower voltage area and for directing power to at least one of the first well, the second well, and the third well.

13. The electrostatic discharge circuit of claim 12, wherein the lower voltage area helps maintain voltage uniformity.

14. An electrostatic discharge circuit between a first pad and a second pad, comprising:

an electrostatic discharge circuit element, including a bipolar transistor path, and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.

15. The electrostatic discharge circuit of claim 14, wherein the resistor path includes a switching pathway.

16. The electrostatic discharge circuit of claim 15, wherein the switching pathway is located between adjacent contact holes.

17. The electrostatic discharge circuit of claim 15, the switching pathway having a width sufficient to form a full depletion region across the switching pathway.

18. The electrostatic discharge circuit of claim 14, wherein the bipolar transistor path includes a silicon controlled rectifier.

19. The electrostatic discharge circuit of claim 18, wherein the silicon controlled rectifier includes a pnp bipolar transistor and an npn bipolar transistor.

20. The electrostatic discharge circuit of claim 19, wherein the silicon controlled rectifier further including a first resistor corresponding to the npn bipolar transistor and a second resistor corresponding to the pnp bipolar transistor.

21. The electrostatic discharge circuit of claim 20, wherein the pnp bipolar transistor and the npn bipolar transistor operate in a positive-feedback condition to push the silicon controlled rectifier into a regeneration mode to form a low impedance discharge channel to shunt the electrostatic current.

22. The electrostatic discharge circuit of claim 15, further comprising:

an isolation layer defining an active region including the switching pathway and a guard ring, for defining a lower voltage area.

23. A method of dissipating an electrostatic current caused by an electrostatic discharge event, comprising:

alternately discharging the electrostatic current through a bipolar transistor path and a resistor path.

24. The method of claim 23, wherein alternately discharging the electrostatic current through the bipolar transistor path includes,

inducing current flow through at least two bipolar transistors to create a positive-feedback condition to form a low impedance discharge channel to shunt the electrostatic current.

25. The method of claim 24, wherein alternately discharging the electrostatic current through the resistor path includes,

forming a depletion region near an np junction due to the positive-feedback condition, to allow current flow through at least one switching pathway of the resistor path.

26. The method of claim 25, wherein alternately discharging the electrostatic current through the resistor path further includes,

forming a full depletion region near the np junction, which cuts off the current flow through the at least one switching pathway of the resistor path.

27. The method of claim 26, wherein alternately discharging the electrostatic current through the bipolar transistor path further includes,

inducing the current flow through the at least two bipolar transistors again, in response to the cutting off the current flow through the at least one switching pathway of the resistor path.

28. An electrostatic discharge circuit comprising:

a first pad and a second pad; and

an electrostatic discharge circuit element, connected between the first pad and the second pad, the electrostatic discharge circuit element including means for alternately discharging an electrostatic current through a bipolar transistor path and a resistor path.

29. An electrostatic discharge circuit comprising:

a first pad and a second pad; and

an electrostatic discharge circuit element, connected between the first pad and the second pad, the electrostatic discharge circuit element including means for controlling a voltage across the electrostatic discharge circuit element between a trigger voltage and a hold voltage to discharge an electrostatic current.