Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition

• US 20060176040A1
• Filed: 01/04/2006
• Published: 08/10/2006
• Est. Priority Date: 01/05/2005
• Status: Active Grant

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: FYRE Storm Incorporated (Maxlinear Incorporated)
• Inventors: Kernahan, Kent, Lambert, Craig Norman, Thomas, John Carl
• Granted Patent: US 7,543,163 B2
• Time in Patent Office: Days
• US Class Current: 323/299
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.

Claims

1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:

(a) using a set of one or more, low-powered analog comparators to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes;

(b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and

(c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

2. The method of claim 1 wherein:

(a.1) one or more of said alert-worthy changes of condition are detected by comparing a respectively monitored analog signal relative to a correspondingly supplied reference signal.

3. The method of claim 2 and further comprising:

(a.2) while said system is in its more normal, higher powered mode rather than the relatively low-powered mode, adjusting at least one of said reference signals as respectively supplied to one or more given ones of the low-powered analog comparators, where said adjusting counter-compensates for one or more errors in signaling pathways of each respective one of the given low-powered analog comparators where said counter-compensated-for errors include at least one of a comparator offset error and a DAC offset error.

4. The method of claim 1 wherein:

(a.1) one or more of said alert-worthy changes of condition is defined as a unidirectional crossing of the respectively monitored condition either above or below a predefined threshold.

5. The method of claim 4 and further comprising:

(a.2) programmably defining said predefined threshold prior to commencement of said monitoring and while said system is not in its relatively low-powered mode.

6. The method of claim 1 wherein:

(a.1) one or more of said alert-worthy changes of condition is defined as a departure of the monitored condition from a predefined containment range.

7. The method of claim 6 and further comprising:

(a.2) programmably defining said predefined containment range prior to commencement of said monitoring and while said system is not in its relatively low-powered mode.

8. The method of claim 1 and further comprising:

(d) reducing power draw of the first logical responding unit prior to commencement of said low power monitoring by stopping supply of clock signals to the first logical responding unit while leaving the first logical responding unit in a state where it will be awakened immediately or within a few number of start up ticks of the quick start oscillator following start up of said quick start oscillator, where said few number is less than or equal to 100.

9. The method of claim 8 wherein said few number is 8 or less.

10. The method of claim 8 wherein said few number is in the range 2 to 100 inclusive.

11. The method of claim 8 wherein said system includes one or more further logical units in addition to said first logical responding unit and said method includes:

(e) reducing power draw of the one or more further logical units prior to commencement of said low power monitoring by stopping supply of clock signals to said further logical units while leaving the one or more further logical responding units in respective states where they can be awakened by start of their respectively stopped clock signals; and

(f) keeping the one or more further logical units in their respective unclocked, asleep states while the first logical responding unit awakens to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

12. The method of claim 1 and further comprising:

(c.1) upon using the started up oscillator to clock the first logical responding unit, further causing the first logical responding unit to determine which, if any, low-powered analog comparator signaled the alert-worthy change of condition that led to the start up of said oscillator.

13. The method of claim 1 wherein the quickly started oscillator is a variable frequency oscillator, and the method further comprises:

(b.1) comparing the output frequency of the started variable frequency oscillator to a predefined target value, and if the frequency comparison indicates an off target condition, adjusting the output frequency of the started variable frequency oscillator towards convergence with the target value.

14. The method of claim 13 wherein the target value represents a frequency which is at least 10 times greater than a reference frequency of a supplied reference clock signal and the target value is programmably set.

15. The method of claim 13 and further comprising:

(b.2) recording data representing the state of the variable frequency oscillator after said adjusting of the output frequency so that the variable frequency oscillator can be restarted in a state defined by the recorded data when restarting in response to one of said analog comparators detecting a next alert-worthy change of condition.

16. The method of claim 1 wherein the quickly started oscillator is a variable frequency oscillator, and the method further comprises:

(c.1) preventing the quickly started up oscillator from clocking the first logical responding unit until the quickly started up oscillator has a frequency below a predefined maximum frequency.

17. The method of claim 16 and further comprising:

(c.2) starting the quickly started up oscillator in a state where the output frequency of the started up oscillator can be greater than said predefined maximum frequency.

18. A system having a relatively low-powered, sleep mode and one or more system vital conditions that may require monitoring during the sleep mode to assure that the system can be awakened without loss of operational states developed prior to entry into the low-powered, said system also having a higher powered mode and comprising:

(a) one or more, low-powered analog comparators coupled to monitor said one or more system vital conditions for respectively pre-defined, alert-worthy changes of condition;

(b) one or more quick-start oscillators, each operatively coupled to one or more of said analog comparators for quickly starting up within one millisecond or less in response to a detecting of an alert-worthy change of condition by a corresponding one of said analog comparators; and

(c) a first logic unit that can be started up out of a respective first low power state by activation of at least one of said quick-start oscillators, the clocking of the first logic unit enabling the first logic unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

19. The system of claim 18 wherein:

(a.1) at least a given one of said low-powered analog comparators is coupled to receive a respective monitored analog signal and a corresponding reference signal against which the respective monitored analog signal is to be compared within the given analog comparator.

20. The system of claim 19 and further comprising:

(a.2) a digital-to-analog converter (DAC) operatively coupled to produce said corresponding reference signal.

21. The system of claim 20 and further comprising:

(a.3) a DAC-controlling memory operatively coupled to supply a digital input word to said DAC for thereby producing the corresponding reference signal; and

(a.4) an analog-to-digital converter (ADC) operatively coupled to said given analog comparator for measuring an output of the given analog comparator when a given digital input word is supplied to said DAC for thereby producing the corresponding reference signal.

22. The system of claim 21 and further comprising:

(a.5) input shorting means operatively coupled to the given analog comparator for temporarily shorting the ADC-measured output of the given analog comparator to an input thereof so that the given analog comparator behaves substantially as a unity gain amplifier.

23. The system of claim 21 and further comprising:

(a.5) a multiplexer operatively coupled to the analog-to-digital converter (ADC) so that the ADC can be used to measure a supply voltage and relay the measurement data to the first logic unit.

24. The system of claim 23 wherein the ADC is operatively coupled to receive a clock signal output by at least one of the awakened quick-start oscillators.

25. The system of claim 18 wherein:

(a.1) at least a given one of said low-powered analog comparators is configured to more strongly react to a first unidirectional crossing of a respectively monitored condition past a predefined threshold than to react to an opposed second unidirectional crossing of the respectively monitored condition past the predefined threshold thereby causing the first unidirectional crossing to function as an alert-worthy change of condition.

26. The system of claim 18 and further comprising:

(d) power down means for placing one or more of the low-powered analog comparators in respective power down modes.

27. The system of claim 18 and further comprising:

(d) a second logic unit that is not awakened out of a respective second low power state by activation of at least one of said quick-start oscillators that starts up the first logic unit out of its respective first low power state.

28. The system of claim 18 and further comprising:

(d) alert source identifying logic, operatively coupled to the first logic unit for allowing the first logic unit to determine which, if any, of the low-powered analog comparators signaled an alert-worthy change of condition that led to the start up of at least one of said quick-start oscillators and consequential start up of the first logic unit.

29. The system of claim 18 wherein at least a given one quickly started oscillator (QSO) includes a variable frequency oscillator, and the given QSO further comprises:

(b.1) a frequency calibrator structured to compare the output frequency of the variable frequency oscillator to a predefined target value, and if the frequency comparison indicates an off target condition, to adjust the output frequency of the variable frequency oscillator towards convergence with the target value.

30. The system of claim 29 wherein the given QSO further comprises:

(b.2) adjustment memory for storing data representing a frequency adjustment earlier made by the frequency calibrator, the adjustment memory being operatively coupled to the variable frequency oscillator such that when the given QSO is restarted or is further calibrated, results of the earlier made frequency adjustment can be used for making a next frequency adjustment.

31. The system of claim 29 and further comprising:

(d) a low frequency reference clock operatively coupled to the frequency calibrator of the given QSO for allowing the frequency calibrator to compare the output frequency of the variable frequency oscillator against a reference frequency of a reference clock signal produced by the low frequency reference clock, wherein the target value represents a frequency which is at least 10 times greater than said reference frequency of the low frequency reference clock.

32. The system of claim 31 and further comprising:

(e) target storage for storing the target value as a programmably set data signal.

33. The system of claim 32 and further comprising:

(f) preset storage for storing preset data representing an initial state of the variable frequency oscillator from which the variable frequency oscillator is to be calibrated to attain a target frequency represented by the target value.

34. The system of claim 18 and further comprising:

(a.1) one or more programmable storage units for programmably defining said alert-worthy changes of condition to be detected by respective ones of said low-powered analog comparators.

35. The system of claim 34 wherein:

(a.2) said one or more programmable storage units are operatively coupled to an error compensating means that adjusts the programmable definition of the alert-worthy change of condition to counter-compensate for an offset error and/or other error associated with one or both of the analog comparator which monitors the respectively monitored condition and a digital-to-analog converter (DAC) which converts into an analog counterpart, the programmable definition of the alert-worthy change of condition.

36. A method of monitoring voltage while maintaining a relatively low power state, the method comprising:

(a) receiving a first voltage signal at a first input terminal of a first differential amplifier;

(b) receiving a second voltage signal at a second input terminal of the first differential amplifier;

where said first differential amplifier is operatively coupled to an output buffer having an output node;

(c) in response to said second voltage signal dropping below said first voltage signal switching said output buffer with use of an output boost effect such that said output node of the output buffer is driven rapidly, due to the boost effect, from a first output state indicative of the second voltage signal being greater than the first voltage signal toward a second output state indicative of the second voltage signal being less than or equal to the first voltage signal, where such a boost effect is not provided for driving said output node toward the first output state, and where said first and second output states are separated from one another by a meta state, wherein the crossing of said meta state urges the output node of the output buffer to continue towards that state of the first and second output states which is on the post-crossing side of the meta state; and

(d) in response to said crossing of the meta-state by the output node of the output buffer, discontinuing said boost effect so as to thereby reduce power draw by the output buffer.

37. The voltage monitoring method of claim 36 and further comprising:

(e) in response to said crossing of the meta-state by the output node of the output buffer toward the second output state, activating an input hysteresis effect so as to thereby urge the output node of the output buffer to continue towards said second output state.

38. The voltage monitoring method of claim 37 and further comprising:

(f) in response to said output node of the output buffer being in the first output state, keeping said input hysteresis effect deactivated.

39. The voltage monitoring method of claim 38 wherein:

(b.1) the output buffer has a current sourcing portion and a current sinking portion both coupled to the output node; and

(c.1) said response to said second voltage signal dropping below said first voltage signal includes switching said current sourcing portion of the output buffer with a boost effect applied to the current sourcing portion of the output buffer.

40. The voltage monitoring method of claim 36 and further comprising:

(e) in response to said output node of the output buffer switching to the second output state indicative of the second voltage signal being less than or equal to the first voltage signal, starting an oscillator.

41. The voltage monitoring method of claim 40 and further comprising:

(f) after the starting of said oscillator, temporarily switching the first differential amplifier and the output buffer into a power-down mode.

42. An analog-to-digital comparator having asymmetrical responsiveness to one of its analog input signals being different from another of its input signals, the comparator comprising:

(a) a first differential amplifier having a first input terminal for receiving a respective first input voltage signal, a second input terminal for receiving a respective second input voltage signal, first and second insulated gate input transistors having respective first and second gates operatively coupled respectively to the first and second input terminals and having respective first and second drains coupled respectively at least to first and second, current sinking transistors;

(b) an output buffer operatively coupled to be driven by said first differential amplifier, the output buffer having an output node and first and second output transistors respectively coupled to source charge into the output node and sink charge away from the output node,

(b.1) the output buffer further including a third output transistor coupled to source a boost charge into the output node, and

(b.2) the output buffer further including an asymmetrical activator operatively coupled to the third output transistor and to the output node for selectively activating the third output transistor to supply said boost charge into the output node when voltage of the output node is below a predefined, meta-level and for selectively deactivating the third output transistor when voltage of the output node is above the predefined meta-level; and

(c) a hysteresis circuit, operatively coupled to said asymmetrical activator and to the first gate of the first insulated gate input transistor, and configured to urge the first insulated gate input transistor toward shutoff so as to thereby reduce sensitivity of the first differential amplifier to input noise.

43. The analog-to-digital comparator of claim 42 wherein:

(c.1) the hysteresis circuit includes a voltage dropping resistance interposed between said first gate of the first insulated gate input transistor and said first input terminal.

44. The analog-to-digital comparator of claim 43 wherein:

(c.2) the hysteresis circuit includes a current source operatively coupled to flow a predetermined magnitude of current through said voltage dropping resistance.

45. The analog-to-digital comparator of claim 42 and further comprising:

(d) a common-mode feedback mechanism operatively coupled to said first and second, current sinking transistors for urging the first and second, current sinking transistors to operate in a saturation part of their respective operating characteristics.

46. The analog-to-digital comparator of claim 42 and further comprising:

(d) power-down circuitry operatively coupled to at least one of said first differential amplifier, said output buffer and said hysteresis circuit, for selectively shutting off current flow through said at least one of the circuits to which the power-down circuitry is operatively coupled when the comparator is switched into a power down mode.

47. The analog-to-digital comparator of claim 42 and further comprising:

(d) calibration mode circuitry for selectively coupling said output node to an inversion function providing one of said first and second insulated gate input transistors when the comparator is switched into a voltage follower mode.

48. The analog-to-digital comparator of claim 47 wherein:

(d.1) said calibration mode circuitry includes a selectively activated filter that is activated to reduce oscillatory behavior of the comparator when the comparator is switched into said voltage follower mode.

49. A method for quickly starting a digital oscillator and causing it to oscillate at or substantially near a specified target frequency, the method comprising:

(a) in response to receipt of a start signal, closing a feedback loop of a variable frequency ring oscillator;

(b) in response to receipt of a variable, digital control signal, generating a corresponding analog control signal and applying the analog control signal to said variable frequency ring oscillator to thereby variably establish a steady state oscillating frequency of the ring oscillator;

(c) in response to receipt of said start signal, beginning to compare the established steady state oscillating frequency of the ring oscillator against a target frequency defined by a supplied, digital target signal; and

(d) in response to detection by said comparing step (c) of an error existing between the target frequency and the established steady state oscillating frequency;

updating said digital control signal so as to reduce the amount of error between the target frequency and the established steady state oscillating frequency.

50. The quick start method of claim 49 wherein:

(c.1) said step of beginning to compare the established steady state oscillating frequency of the ring oscillator against the target frequency is not commenced until a predetermined, nonzero number of cycles of the ring oscillator have occurred after said closing of the feedback loop of the variable frequency ring oscillator.

51. The quick start method of claim 50 wherein:

(c.1a) said nonzero number of cycles is at least four.

52. The quick start method of claim 49 wherein:

(c.1) said step of beginning to compare the established steady state oscillating frequency of the ring oscillator includes;

(c.1a) receiving a reference clock signal of substantially lower frequency than said target frequency;

(c.1b) counting how many cycles of the established oscillating frequency of the ring oscillator fit within a period of the reference clock signal or within a predefined and accurately marked subperiod of the reference clock signal; and

(c.1c) comparing the count obtained in said step (c.1b) against a second count value representing the target frequency.

53. The quick start method of claim 49 wherein:

(d.1) said step of updating the digital control signal includes;

(d.1a) supplying a current version of the digital control signal to an adder;

(d.1b) in response to a signal indicating whether the established oscillating frequency is greater or less than the target frequency, correspondingly causing the adder to subtract or add respective predetermined amounts from the supplied current version of the digital control signal; and

(d.1c) recording the result output by said adder as a new current version of the digital control signal.

54. The quick start method of claim 49 and further comprising:

(e) tapping complementary and respective, first and second delay points within said ring oscillator to obtain respective first and second tapped signals;

(f) delaying one of the tapped signals to thereby bring the delayed tapped signal into phase aligned but opposed polarity relation with the other of the tapped signals; and

(g) applying the delayed tapped signal and the other of the tapped signals to opposed input nodes of a differential output buffer.

55. The quick start method of claim 49 and further comprising:

(e) storing said variable, digital control signal in a memory accessed by said step (b).

56. The quick start method of claim 49 and further comprising:

(f) in generating said corresponding analog control signal, preventing the corresponding digital control signal from being incremented or decremented, wrap-around style beyond one or more boundaries of a predefined, allowable range of values.

57. A method of starting a voltage controlled oscillator (VCO) and causing it to quickly reach a steady state oscillating mode after start up where the VCO oscillates in said steady state mode at or substantially near a specified target frequency and the VCO has a controllable loop gain, the method comprising:

(a) controlling said controllable loop gain to thereby establish a positive feedback loop in the VCO to thereby initiate oscillations within the VCO;

(b) at the time of said establishing (a) of the positive feedback loop, first applying a control voltage of a first control voltage magnitude to the VCO, where the first applied control voltage has a magnitude greater than a second control voltage magnitude and where the VCO will oscillate in said steady state mode at or substantially near the specified target frequency when said second control voltage magnitude is applied thereto; and

(c) causing the control voltage applied to the VCO to decrease from said first control voltage magnitude toward said second control voltage magnitude.

58. The VCO starting method of claim 57 and further comprising:

(d) aside from said establishing (a) of the positive feedback loop and said causing (c) of the control voltage to decrease from the first control voltage magnitude toward the second control voltage magnitude, maintaining essentially all other frequency-affecting parameters of the VCO in essentially steady or fixed state so that time for attainment of said steady state mode at or substantially near the specified target frequency is essentially dependent on just said establishing (a) of the positive feedback loop and said causing (c) of the control voltage to change in magnitude.

59. The VCO starting method of claim 57 wherein:

(a.1) said controlling of the controllable loop gain includes switching a digital gate from a first state to a second state, where the second state establishes the positive feedback loop.

60. The VCO starting method of claim 57 wherein:

(a.1) said controlling of the controllable loop gain includes closing an open loop ring oscillator.

61. The VCO starting method of claim 57 wherein:

(b.1) said applying to the VCO of the first control voltage magnitude and said reducing of the control voltage toward said second magnitude includes using an NMOS transistor to supply a current of increasing magnitude to the VCO, said supplied current increasing in magnitude as said control voltage reduces towards said second magnitude.

62. The VCO starting method of claim 57 wherein:

(b.1) said applying to the VCO of the first control voltage magnitude and said reducing of the control voltage toward said second magnitude includes using a capacitor to supply charge to the VCO.

63. The VCO starting method of claim 57 wherein:

(b.1) said applying to the VCO of the first control voltage magnitude includes using a digital-to-analog converter (DAC) and an insulated gate transistor having its insulated gate coupled to an output of the DAC for establishing said first control voltage magnitude.

64. The VCO starting method of claim 57 and further comprising:

(d) using one or more insulated gate transistors to isolate one or more output stages of the started up VCO from possible variations in output loading.

65. A quick start oscillator (QSO) comprising:

(a) a voltage controlled oscillator circuit (VCO) having a controllable gain loop that can be digitally switched from a below unity gain state to an above unity gain state so as to thereby establish with said switching, a positive feedback effect and to thereby initiate oscillations within the VCO;

(b) a control voltage applying circuit, operatively coupled to the VCO and configured to first apply a control voltage of a first control voltage magnitude to the VCO at the time said controllable gain loop that is digitally switched from its below unity gain state to its above unity gain state, the control voltage applying circuit being further configured to change the applied control voltage from said first control voltage magnitude towards a second control voltage magnitude where the second control voltage magnitude will cause the VCO to oscillate in a steady state mode at or substantially near a specified target frequency; and

(c) a digital-to-analog converter (DAC) operatively coupled to said control voltage applying circuit for digitally defining the first control voltage magnitude that said control voltage applying circuit will apply to the VCO at the time said controllable gain loop that is digitally switched to its above unity gain state.

66. The quick start oscillator (QSO) of claim 65 wherein:

(a.1) said VCO includes a ring oscillator having at least five inverter stages.

67. The quick start oscillator (QSO) of claim 66 wherein:

(a.2) said VCO includes an output buffer having two or more insulated gate transistors respectively coupled to distributed output nodes among said at least five inverter stages.

68. The quick start oscillator (QSO) of claim 65 wherein:

(b.1) said control voltage applying circuit includes first and second insulated gate transistors, the first insulated gate transistor of the control voltage applying circuit having its gate operatively coupled to said DAC, the second insulated gate transistor of the control voltage applying circuit having its source operatively coupled to said VCO.

69. The quick start oscillator (QSO) of claim 68 wherein:

(b.2) said control voltage applying circuit further includes first and capacitors, the first capacitor being coupled to an insulated gate of the second insulated gate transistor and the second capacitor being coupled to the source of the second insulated gate transistor.

70. The quick start oscillator (QSO) of claim 65 and further comprising:

(d) a digital memory operatively coupled to said DAC for applying a predetermined, digital control signal to the DAC prior to said controllable gain loop being digitally switched to its above unity gain state so that the DAC can output a corresponding analog control signal to the control voltage applying circuit prior to said controllable gain loop being digitally switched to its above unity gain state.

71. A digital-to-analog converter (DAC) for converting a supplied digital input signal into an analog output signal, said DAC comprising:

(a) first and second current collecting lines;

(b) a first plurality of current sources;

(c) a second plurality of digitally controlled, segment switches each having a first terminal for receiving a source current from a corresponding one of said current sources, a second terminal for outputting at least a first part of the received source current in a first mode of the segment switch to the first current collecting line, and a third terminal for outputting at least a second part of the received source current in a given second mode of the segment switch to the second current collecting line;

(d) a voltage equalizing circuit, operatively coupled to the first and second current collecting lines and configured to cause said first and second current collecting lines to have essentially same voltages on them.

72. The DAC of claim 71 and further comprising:

(e) a first current mirror, operatively coupled to the first current collecting line for producing a mirrored replica current equal to, or scaled to the current carried by the first current collecting line.

73. The DAC of claim 72 and further comprising:

(f) a current to voltage converter operatively coupled to the first current mirror, for converting the mirrored replica current into a resistance-defined output voltage.

74. The DAC of claim 73 and further comprising:

(g) a reference voltage supply operatively coupled to the current to voltage converter for establishing a base magnitude for said resistance-defined output voltage when said mirrored replica current is essentially at zero.