Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition
First Claim
1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:
- (a) using a set of one or more, low-powered analog comparators to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes;
(b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and
(c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.
4 Assignments
0 Petitions
Accused Products
Abstract
A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.
-
Citations
74 Claims
-
1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:
-
(a) using a set of one or more, low-powered analog comparators to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes;
(b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and
(c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A system having a relatively low-powered, sleep mode and one or more system vital conditions that may require monitoring during the sleep mode to assure that the system can be awakened without loss of operational states developed prior to entry into the low-powered, said system also having a higher powered mode and comprising:
-
(a) one or more, low-powered analog comparators coupled to monitor said one or more system vital conditions for respectively pre-defined, alert-worthy changes of condition;
(b) one or more quick-start oscillators, each operatively coupled to one or more of said analog comparators for quickly starting up within one millisecond or less in response to a detecting of an alert-worthy change of condition by a corresponding one of said analog comparators; and
(c) a first logic unit that can be started up out of a respective first low power state by activation of at least one of said quick-start oscillators, the clocking of the first logic unit enabling the first logic unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
-
-
36. A method of monitoring voltage while maintaining a relatively low power state, the method comprising:
-
(a) receiving a first voltage signal at a first input terminal of a first differential amplifier;
(b) receiving a second voltage signal at a second input terminal of the first differential amplifier;
where said first differential amplifier is operatively coupled to an output buffer having an output node;
(c) in response to said second voltage signal dropping below said first voltage signal switching said output buffer with use of an output boost effect such that said output node of the output buffer is driven rapidly, due to the boost effect, from a first output state indicative of the second voltage signal being greater than the first voltage signal toward a second output state indicative of the second voltage signal being less than or equal to the first voltage signal, where such a boost effect is not provided for driving said output node toward the first output state, and where said first and second output states are separated from one another by a meta state, wherein the crossing of said meta state urges the output node of the output buffer to continue towards that state of the first and second output states which is on the post-crossing side of the meta state; and
(d) in response to said crossing of the meta-state by the output node of the output buffer, discontinuing said boost effect so as to thereby reduce power draw by the output buffer. - View Dependent Claims (37, 38, 39, 40, 41)
-
-
42. An analog-to-digital comparator having asymmetrical responsiveness to one of its analog input signals being different from another of its input signals, the comparator comprising:
-
(a) a first differential amplifier having a first input terminal for receiving a respective first input voltage signal, a second input terminal for receiving a respective second input voltage signal, first and second insulated gate input transistors having respective first and second gates operatively coupled respectively to the first and second input terminals and having respective first and second drains coupled respectively at least to first and second, current sinking transistors;
(b) an output buffer operatively coupled to be driven by said first differential amplifier, the output buffer having an output node and first and second output transistors respectively coupled to source charge into the output node and sink charge away from the output node, (b.1) the output buffer further including a third output transistor coupled to source a boost charge into the output node, and (b.2) the output buffer further including an asymmetrical activator operatively coupled to the third output transistor and to the output node for selectively activating the third output transistor to supply said boost charge into the output node when voltage of the output node is below a predefined, meta-level and for selectively deactivating the third output transistor when voltage of the output node is above the predefined meta-level; and
(c) a hysteresis circuit, operatively coupled to said asymmetrical activator and to the first gate of the first insulated gate input transistor, and configured to urge the first insulated gate input transistor toward shutoff so as to thereby reduce sensitivity of the first differential amplifier to input noise. - View Dependent Claims (43, 44, 45, 46, 47, 48)
-
-
49. A method for quickly starting a digital oscillator and causing it to oscillate at or substantially near a specified target frequency, the method comprising:
-
(a) in response to receipt of a start signal, closing a feedback loop of a variable frequency ring oscillator;
(b) in response to receipt of a variable, digital control signal, generating a corresponding analog control signal and applying the analog control signal to said variable frequency ring oscillator to thereby variably establish a steady state oscillating frequency of the ring oscillator;
(c) in response to receipt of said start signal, beginning to compare the established steady state oscillating frequency of the ring oscillator against a target frequency defined by a supplied, digital target signal; and
(d) in response to detection by said comparing step (c) of an error existing between the target frequency and the established steady state oscillating frequency;
updating said digital control signal so as to reduce the amount of error between the target frequency and the established steady state oscillating frequency. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56)
-
-
57. A method of starting a voltage controlled oscillator (VCO) and causing it to quickly reach a steady state oscillating mode after start up where the VCO oscillates in said steady state mode at or substantially near a specified target frequency and the VCO has a controllable loop gain, the method comprising:
-
(a) controlling said controllable loop gain to thereby establish a positive feedback loop in the VCO to thereby initiate oscillations within the VCO;
(b) at the time of said establishing (a) of the positive feedback loop, first applying a control voltage of a first control voltage magnitude to the VCO, where the first applied control voltage has a magnitude greater than a second control voltage magnitude and where the VCO will oscillate in said steady state mode at or substantially near the specified target frequency when said second control voltage magnitude is applied thereto; and
(c) causing the control voltage applied to the VCO to decrease from said first control voltage magnitude toward said second control voltage magnitude. - View Dependent Claims (58, 59, 60, 61, 62, 63, 64)
-
-
65. A quick start oscillator (QSO) comprising:
-
(a) a voltage controlled oscillator circuit (VCO) having a controllable gain loop that can be digitally switched from a below unity gain state to an above unity gain state so as to thereby establish with said switching, a positive feedback effect and to thereby initiate oscillations within the VCO;
(b) a control voltage applying circuit, operatively coupled to the VCO and configured to first apply a control voltage of a first control voltage magnitude to the VCO at the time said controllable gain loop that is digitally switched from its below unity gain state to its above unity gain state, the control voltage applying circuit being further configured to change the applied control voltage from said first control voltage magnitude towards a second control voltage magnitude where the second control voltage magnitude will cause the VCO to oscillate in a steady state mode at or substantially near a specified target frequency; and
(c) a digital-to-analog converter (DAC) operatively coupled to said control voltage applying circuit for digitally defining the first control voltage magnitude that said control voltage applying circuit will apply to the VCO at the time said controllable gain loop that is digitally switched to its above unity gain state. - View Dependent Claims (66, 67, 68, 69, 70)
-
-
71. A digital-to-analog converter (DAC) for converting a supplied digital input signal into an analog output signal, said DAC comprising:
-
(a) first and second current collecting lines;
(b) a first plurality of current sources;
(c) a second plurality of digitally controlled, segment switches each having a first terminal for receiving a source current from a corresponding one of said current sources, a second terminal for outputting at least a first part of the received source current in a first mode of the segment switch to the first current collecting line, and a third terminal for outputting at least a second part of the received source current in a given second mode of the segment switch to the second current collecting line;
(d) a voltage equalizing circuit, operatively coupled to the first and second current collecting lines and configured to cause said first and second current collecting lines to have essentially same voltages on them. - View Dependent Claims (72, 73, 74)
-
Specification