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Method and system for programming and driving active matrix light emitting devcie pixel

  • US 20060176250A1
  • Filed: 12/07/2005
  • Published: 08/10/2006
  • Est. Priority Date: 12/07/2004
  • Status: Active Grant
First Claim
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1. A method of programming and driving a display system, the display system includes:

  • a display array having a plurality of pixel circuits arranged in row and column, each pixel circuit having;

    a light emitting device having a first terminal and a second terminal, the first terminal of the lighting device being connected to a voltage supply electrode;

    a capacitor having a first terminal and a second terminal;

    a switch transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the switch transistor being connected to a select line, the first terminal of the switch transistor being connected to a signal line for transferring voltage data, the second terminal of the switch transistor being connected to the first terminal of the capacitor; and

    a driving transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the driving transistor being connected to the second terminal of the switch transistor and the first terminal of the capacitor at a first node (A), the first terminal of the driving transistor being connected to the second terminal of the light emitting device and the second terminal of the capacitor at a second node (B), the second terminal of the driving transistor being connected to a controllable voltage supply line;

    a driver for driving the select line, the controllable voltage supply line and the signal line to operate the display array;

    the method comprising the steps of;

    at a programming cycle, at a first operating cycle, charging the second node at a first voltage defined by (VREF−

    VT) or (−

    VREF+VT), where VREF represents a reference voltage and VT represents a threshold voltage of the driving transistor;

    at a second operating cycle, charging the first node at a second voltage defined by (VREF+VP) or (−

    VREF+VP) so that the difference between the first and second voltages is stored in the storage capacitor, where VP represents a programming voltage;

    at a driving cycle, applying the voltage stored in the storage capacitor to the gate terminal of the driving transistor.

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