Clock generating method and clock generating circuit

• US 20060176933A1
• Filed: 01/13/2006
• Published: 08/10/2006
• Est. Priority Date: 01/14/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakamura, Takashi, Uemura, Yasuhiro, Katsushima, Akio, Funatsu, Makoto
• Granted Patent: US 7,580,443 B2
• Time in Patent Office: Days
• US Class Current: 375/130
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Claims

1. A clock generating method in which while a PLL (Phase-Locked Loop) circuit and a modulator are employed, a frequency dividing ratio of a feedback-purpose frequency divider in said PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of said modulator to perform a frequency modulation, so that a spectrum is spread, wherein:

said spread spectrum is re-spread by moving a turning point of said modulation profile so as to disperse a degree of frequency.

2. A clock generating method as claimed in claim 1 wherein:

said spread spectrum is re-spread by moving the turning point of said modulation profile based upon a triangle-shaped re-spread modulation profile, the time period of which is longer than that of said modulation profile.

3. A clock generating method as claimed in claim 1 wherein:

said spread spectrum is re-spread by moving the turning point of said modulation profile in accordance with a predetermined sequence under such a condition that said turning point is not concentrated to the same point every time period of said modulation profile, or for a time period longer than a time period of said modulation profile.

4. A clock generating method as claimed in claim 1 wherein:

said spread spectrum is re-spread by moving the turning point of said modulation profile in an irregular manner in accordance with random numbers which are produced every time period of said modulation profile, or for a time period longer than a time period of said modulation profile.

5. A clock generating circuit comprising:

a PLL (Phase-Locked Loop) circuit and a modulator; and

for changing a frequency dividing ratio of a feedback-purpose frequency divider in said PLL circuit in accordance with modulation data produced based upon a modulation profile of said modulator to perform a frequency modulation whereby a spectrum is spread;

wherein;

said modulator is comprised of a multiple modulation profile generating circuit, and moves a turning point of said modulation profile so as to disperse a degree of frequency.

6. A clock generating circuit as claimed in claim 5 wherein:

said modulator is further comprised of;

a Δ

Σ

bit converting circuit and a modulation factor switching circuit;

said Δ

Σ

bit converting circuit performs a pulse width modulation by which a multiple modulation profile outputted by said multiple modulation profile generating circuit is converted into 1 bit; and

said modulation factor switching circuit switches a frequency spread width which is determined based upon both the frequency dividing ratio of said feedback-purpose frequency divider and a value which is added to said frequency dividing ratio in response to the output of said Δ

Σ

bit converting circuit.

7. A clock generating circuit as claimed in claim 6 wherein:

said multiple modulation profile generating circuit is comprised of;

a subtractor, a first comparator, a second comparator, a first up/down counter, and a second up/down counter;

said first up/down counter performs either a count-up operation or a count-down operation for a reference clock in response to either a count-up switching signal or a count-down switching signal, which are outputted by said first comparator, so as to output a modulation profile for a frequency spread;

said second up/down counter performs a counting operation of the output from said first comparator in response to either a count-up switching signal or a count-down switching signal outputted from said second comparator which compares both a minimum shift value and a maximum shift value which determine a range of a re-spread, with the own comparison output; and

said first comparator receives the output signal of said second up/down counter as a minimum comparison value, and also receives as a maximum comparison value, such an output signal which is obtained by subtracting the output signal of said second up/down counter from a predetermined maximum comparison value, so as to control the counting operation of said first up/down counter.

8. A clock generating circuit as claimed in claim 6 wherein:

said multiple modulation profile generating circuit is comprised of;

a subtractor, a comparator, a random number generator, an up/down counter, and a register;

said up/down counter performs either a count-up operation or a count-down operation for a reference clock in response to either a count-up switching signal or a count-down switching signal, which are outputted by said first comparator, so as to output a modulation profile for a frequency spread;

said register acquires random numbers generated by said random number generator in accordance with a count-up switching signal and a count-down switching signal, which are outputted from said comparator; and

said comparator receives the output signal of said register as a minimum comparison value, and also receives as a maximum comparison value, such an output signal which is obtained by subtracting the output signal of said register from a predetermined maximum comparison value, so as to control the counting operation of said up/down counter.

9. A clock generating circuit as claimed in claim 6 wherein:

said Δ

Σ

bit converting circuit is comprised of;

a first adder, a second adder, a quantizer, and a register, and

said Δ

Σ

bit converting circuit selects an arbitrary bit from an output of said register, and feeds back said selected bit to said multiple modulation profile generating circuit as re-spread purpose data;

said multiple modulation profile generating circuit is comprised of;

a subtractor, a comparator, an up/down counter, a first register, and a second register;

said up/down counter performs either a count-up operation or a count-down operation for a reference clock in response to either a count-up switching signal or a count-down switching signal, which are outputted by said first comparator, so as to output a modulation profile for a frequency spread;

said first register acquires the re-spread purpose data formed by said Δ

Σ

bit converting circuit in accordance with said reference clock;

said second register acquires the output signal of said first register in accordance with both the count-up switching signal and the count-down switching signal, which are outputted by said comparator; and

said comparator receives the output signal of said second register as a minimum comparison value, and also receives as a maximum comparison value, such an output signal which is obtained by subtracting the output signal of said second register from a predetermined maximum comparison value, so as to control the counting operation of said up/down counter.