Method and system for preventing cache lines from being flushed until data stored therein is used

• US 20060179174A1
• Filed: 02/02/2005
• Published: 08/10/2006
• Est. Priority Date: 02/02/2005
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Bockhaus, John William, Binford, David
• Application Number:
  US11/049,011
• Publication Number:
  US 20060179174A1
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/303 In peripheral interface, e.g. I/O adapter or channel

Abstract

System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and responsive to a determination that the memory request is not speculative, ensuring that a prefetch lock indicator of a cache line of a cache associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“CRA”) from flushing the associated cache line.

Claims

1. A method of memory utilization in a computer system, the method comprising:

responsive to receipt of a DMA transaction from an entity, determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and

responsive to a determination that the memory request is not speculative, ensuring that a prefetch lock indicator of a cache line of a cache associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“

CRA”

) from flushing the associated cache line.

2. The method of claim 1 further comprising, responsive to a determination that the memory request is speculative, ensuring that a prefetch lock indicator of a cache line associated with the memory request is in an unlocked condition.

3. The method of claim 1 further comprising, responsive to receipt of a DMA transaction from the entity, dividing the received DMA transaction into a number of cache line-sized memory requests.

4. The method of claim 1 further comprising unlocking the prefetch lock indicator responsive to delivery of data stored in the associated cache line to the entity.

5. The method of claim 1 further comprising unlocking the prefetch lock indicator responsive to expiration of a predetermined time period associated with data stored in the associated cache line.

6. The method of claim 1 wherein the determining comprises determining whether the memory request comprises a portion of a PCIX DMA read transaction, wherein if the memory request comprises a portion of a PCIX DMA read transaction, a determination is made that the memory request is not speculative.

7. The method of claim 1 wherein the determining comprises determining whether the memory request is a first memory request of a PCI DMA read transaction, wherein if the memory request is a first memory request of a PCI DMA read transaction, a determination is made that the memory request is not speculative.

8. The method of claim 1 wherein the determining comprises determining whether the memory request comprises a portion of a fixed-length DMA read transaction, wherein if the memory request comprises a portion of a fixed length DMA read transaction, a determination is made that the memory request is not speculative.

9. The method of claim 1 wherein the entity is an I/O device and the cache is an input/output (“

I/O”

) cache memory.

10. The method of claim 1 wherein the cache is a coherent cache memory.

11. A memory utilization method in a computer system, the method comprising:

responsive to receipt of a DMA transaction from an entity, dividing the DMA transaction into at least one cache line-sized memory request;

determining whether the at least one memory request is speculative; and

responsive to a determination that the at least one memory request is not speculative, ensuring that a prefetch lock indicator of a cache line of a cache memory associated with the at least one memory request is in a locked condition, thereby preventing a cache replacement algorithm (“

CRA”

) from flushing the associated cache line.

12. The method of claim 11 further comprising, responsive to a determination that the at least one memory request is not speculative, ensuring that the prefetch lock indicator is in an unlocked condition.

13. The method of claim 12 further comprising unlocking the prefetch lock indicator responsive to delivery of data stored in the associated cache line to the entity.

14. The method of claim 12 further comprising unlocking the prefetch lock indicator responsive to expiration of a predetermined time period associated with data stored in the associated cache line.

15. The method of claim 11 wherein the determining comprises determining whether the memory request comprises a portion of a PCIX DMA read transaction, wherein if the memory request comprises a portion of a PCIX DMA read transaction, a determination is made that the memory request is not speculative.

16. The method of claim 11 wherein the determining comprises determining whether the memory request is a first memory request of a PCI DMA read transaction, wherein if the memory request is a first memory request of a PCI DMA read transaction, a determination is made that the memory request is not speculative.

17. The method of claim 11 wherein the determining comprises determining whether the memory request comprises a portion of a fixed-length DMA read transaction, wherein if the memory request comprises a portion of a fixed length DMA read transaction, a determination is made that the memory request is not speculative.

18. The method of claim 11 wherein the entity is an I/O device and the cache memory is an input/output (“

I/O”

) cache memory.

19. The method of claim 11 wherein the cache memory is a coherent cache memory.

20. A system for memory utilization in a computer, the system comprising:

cache means for storing data in connection with DMA transactions;

means responsive to receipt of a DMA transaction from an entity for determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and

means responsive to a determination that the memory request is not speculative for ensuring that a prefetch lock indicator of a cache line of the cache means associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“

CRA”

) from flushing the associated cache line.

21. The system of claim 20 further comprising means responsive to a determination that the memory request is speculative for ensuring that a prefetch lock indicator of a cache line associated with the memory request is in a unlocked condition.

22. The system of claim 20 further comprising means responsive to receipt of a DMA transaction from the entity for dividing the received DMA transaction into at least one cache line-sized memory request.

23. The system of claim 20 further comprising means for unlocking the prefetch lock indicator responsive to delivery of data stored in the associated cache line to the entity.

24. The system of claim 20 further comprising means for unlocking the prefetch lock indicator responsive to expiration of a predetermined time period associated with data stored in the associated cache line.

25. The system of claim 20 wherein the means for determining comprises means for determining whether the memory request comprises a portion of a PCIX DMA read transaction, wherein if the memory request comprises a portion of a PCIX DMA read transaction, the memory request is not speculative.

26. The system of claim 20 wherein the means for determining comprises means for determining whether the memory request is a first memory request of a PCI DMA read transaction, wherein if the memory request is a first memory request of a PCI DMA read transaction, the memory request is not speculative.

27. The system of claim 20 wherein the means for determining comprises means for determining whether the memory request comprises a portion of a fixed-length DMA read transaction, wherein if the memory request comprises a portion of a fixed length DMA read transaction, the memory request is not speculative.

28. The system of claim 20 wherein the entity is an I/O device and the cache means is an input/output (“

I/O”

) cache memory.

29. The system of claim 20 wherein the cache means is a coherent cache memory.

30. A computer-readable medium operable with a computer including a cache memory for performing DMA transactions in a computer, the medium having stored thereon:

instructions executable by the computer responsive to receipt of a DMA transaction from an entity for determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and

instructions executable by the computer responsive to a determination that the memory request is not speculative for ensuring that a prefetch lock indicator of a cache line of the cache associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“

CRA”

) from flushing the associated cache line.

31. The medium of claim 30 further having stored thereon instructions executable by the computer responsive to a determination that the memory request is speculative for ensuring that a prefetch lock indicator of a cache line associated with the memory request is in a unlocked condition.

32. The medium of claim 30 further having stored thereon instructions executable by the computer responsive to receipt of a DMA transaction from the entity for dividing the received DMA transaction into at least one cache line-sized memory request.

33. The medium of claim 30 further having stored thereon instructions executable by the computer for unlocking the prefetch lock indicator responsive to delivery of data stored in the associated cache line to the entity.

34. The medium of claim 30 further having stored thereon instructions executable by the computer for unlocking the prefetch lock indicator responsive to expiration of a predetermined time period associated with data stored in the associated cache line.

35. The medium of claim 30 wherein the instructions executable by the computer for determining comprise instructions for determining whether the memory request comprises a portion of a PCIX DMA read transaction, wherein if the memory request comprises a portion of a PCIX DMA read transaction, the memory request is not speculative.

36. The medium of claim 30 wherein the instructions executable by the computer for determining comprise instructions for determining whether the memory request is a first memory request of a PCI DMA read transaction, wherein if the memory request is a first memory request of a PCI DMA read transaction, the memory request is not speculative.

37. The medium of claim 30 wherein the instructions executable by the computer for determining comprise instructions for determining whether the memory request comprises a portion of a fixed-length DMA read transaction, wherein if the memory request comprises a portion of a fixed length DMA read transaction, the memory request is not speculative.