Multithread processor and method for operating a multithread processor

• US 20060179291A1
• Filed: 01/06/2006
• Published: 08/10/2006
• Est. Priority Date: 01/07/2005
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Di Gregorio, Lorenzo
• Application Number:
  US11/327,301
• Publication Number:
  US 20060179291A1
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A multithread processor for the data processing of a plurality of threads, each being provided with a dedicated context, comprises a switching table. The switching table receives at least one of an internal exception of a specific context for updating the specific context and for switching from the specific context to a target context of the internal exception or an external exception of a specific context for updating the specific context and for switching from the specific context to a target context of the external exception, and, in a manner dependent thereon, updates at least one of a context parameter set of the context, a context parameter set of the target context of the internal exception, or a context parameter set of the target context of the external exception, and sets a switch parameter set for a sequence control of program instructions to be fetched, so that the multithread processor switches between the context and the target context of at least one of the internal or the external exception without restrictions or cycle loss.

Claims

1. A multithread processor for the data processing of a plurality of threads, each being provided with a dedicated context;

said multithread processor comprising a switching table, which

receives at least one of an internal exception of a specific context for updating said specific context and for switching from said specific context to a target context of said internal exception or an external exception of a specific context for updating said specific context and for switching from said specific context to a target context of said external exception,

and, in a manner dependent thereon,

updates at least one of a context parameter set of said context, a context parameter set of said target context of said internal exception, or a context parameter set of said target context of said external exception, and

sets a switch parameter set for a sequence control of program instructions to be fetched, so that said multithread processor switches between said context and said target context of at least one of said internal or said external exception without restrictions or cycle loss.

2. The multithread processor of claim 1, comprising an instruction fetch pipeline stage for fetching said program instructions from a program instruction memory and an instruction decoding pipeline stage;

said switching table being arranged within said instruction decoding pipeline stage.

3. The multithread processor of claim 1, wherein said switch parameter set is formed from at least one of:

a context flag specifying the current context of said corresponding pipeline stage;

a program instruction address of the next program instruction of said current context of said corresponding pipeline stage,

a squash reset flag specifying processing again subsequent program instructions of said current context of said corresponding pipeline stage;

a kill flag indicating not to take into account jump instructions of a subsequent pipeline stage, which are situated in said current context of said switching table.

4. The multithread processor of claim 1, wherein each of said context parameter sets is formed from at least one of:

a program address of said corresponding context;

a program address of a delay slot instruction of said corresponding context;

a squash flag of the corresponding of said contexts, said squash flag specifying not to process program instructions of said corresponding context;

a flag for specifying a pending program address of said corresponding context;

a flag for specifying a pending delay slot instruction of said corresponding context;

a flag for specifying a number of pending delay slot instructions of said corresponding context.

5. The multithread processor of claim 1, wherein said switching table, upon receiving said internal exception and said external exception, updates said context parameter set of a current of said context, said context parameter set of said target context of said internal exception and said context parameter set of said target context of said external exception in such a way so that said multithread processor switches from said current context to said target context of said external exception, upon occurrence of a blocking of said target context of said external exception to said target context of said internal exception and then, upon occurrence of a blocking of said target context of said internal exception, back to the original of said current context.

6. The multithread processor of claim 2, wherein said instruction decoding pipeline stage comprises a program address table, which buffer-stores a valid context parameter set in each case for each of said contexts of said multithread processor;

said switching table in each case updating said stored context parameter sets of a current of said context of said target context of said internal exception and of said target context of said external exception.

7. The multithread processor of claim 2, comprising at least one further pipeline stage being arranged downstream of said instruction decoding pipeline stage and processing said decoded program instructions.

8. The multithread processor of claim 7, wherein each of said further pipeline stages, if said program instruction processed is a jump instruction, provides a further switch parameter set and a validity signal for specifying a validity of said further switch parameter set.

9. The multithread processor of claim 8, wherein said switch parameter set comprises a squash reset flag specifying processing again subsequent program instructions of said current context of said corresponding pipeline stage;

said squash flag specifying not to process program instructions of said corresponding context; and

said processor comprising a sequence control, which receives said switch parameter set of said instruction decoding pipeline stage and also said further switch parameter sets and said validity signals of said further pipeline stages and, dependent thereon, generates a context parameter specifying which of said contexts is processed next, a program address of said context to be processed next, and said squash reset flag of context to be processed next and transmits them to said instruction fetch pipeline stage.

10. The multithread processor of claim 9, wherein said instruction fetch pipeline stage fetches said next program instruction from said program instruction memory in a manner dependent on said context parameter received by said sequence control and said received associated program address.

11. The multithread processor of claim 1, comprising a buffer memory providing, for each of said contexts of said multithread processor, a sub buffer memory in which at least in each case said program instructions are buffer stored.

12. The multithread processor of claim 11, wherein said program instructions being buffer-stored are delay slot instructions of the corresponding of said contexts.

13. The multithread processor of claim 11, wherein each of said context parameter sets is formed from at least of a squash flag of the corresponding of said contexts, said squash flag specifying not to process program instructions of said corresponding context and wherein said switching table addresses, by means of a memory flag, the respective of said sub buffer memories for buffer-storing said program instructions with a corresponding of said context parameters and the corresponding of said squash reset flags of said corresponding context.

14. The multithread processor of claim 2, wherein said instruction decoding pipeline stage comprises an instruction decoder for decoding said fetched program instructions.

15. The multithread processor of claim 14, comprising a buffer memory providing, for each of said contexts of said multithread processor, a sub buffer memory in which at least in each case said program instructions are buffer stored;

said buffer-stored program instructions being delay slot instructions of the corresponding of said contexts.

16. The multithread processor of claim 15, wherein each of said context parameter sets is formed from at least of a squash flag of the corresponding of said contexts, said squash flag specifying not to process program instructions of said corresponding context and wherein said instruction decoder receives said context parameter, said program instruction addressed by said program address and fetched from said program instruction memory, and said squash reset flag from said buffer memory and also said flag for specifying said number of delay slot instructions of said context to be processed from said program address table, and, in a manner dependent thereon, updates said flag for specifying said number of delay slot instructions, said address of said delay slot instruction of said context to be processed and said address of said pending delay slot instruction of said context to be processed and transmits them to said program address table.

17. The multithread processor of claim 16, wherein said instruction decoder, in each clock cycle, reads out said program instruction of said current context and said associated squash reset flag from said buffer memory and sets said squash flag of said current context to a negative logic signal level if said squash reset flag read-out has a positive logic signal level.

18. The multithread processor of claim 17, wherein said instruction decoder, in each clock cycle in which said squash flag of said current context is set to said positive logic signal level, writes NOP instructions to said respective sub buffer memory for said current context of said buffer memory.

19. The multithread processor of claim 17, wherein said instruction decoder, in the case of said positive signal level of said flag for specifying said number of delay slot instructions of said current context, sets said next program address to said address of said delay slot instruction of said current context if said flag for specifying a pending delay slot instruction of said current context has said positive signal level.

20. The multithread processor of claim 17, wherein said instruction decoder in the case of said positive signal level of said flag for specifying said number of delay slot instructions of said current context and said negative signal level of said flag for specifying a pending program address of said current context, sets said next program address to said program address of said current context if said flag for specifying a pending program address has said positive signal level.

21. The multithread processor of claim 17, wherein said instruction decoder, in the case of said positive signal level of said flag for specifying the number of delay slot instructions of said current context, said negative signal level of said flag for specifying a pending program address of said current context and said negative signal level of said flag for specifying a pending program address of said current context, sets said next program address to said program address of said current context incremented by one.

22. The multithread processor of claim 9, wherein said sequence control receives said switch parameter set of said instruction decoding pipeline stage and also said further switch parameter sets and said validity signals of said further pipeline stages and, in a manner dependent thereon, in each case determines a lowest pipeline stage of said pipeline for each of said contexts of said multithread processor which processes said jump instruction of the respective of said contexts.

23. The multithread processor of claim 22, wherein said sequence control, in a manner dependent on said determined lowest pipeline stage of said current context flag, determines said context parameter of said next context to be processed, said program address of said next context to be processed and said squash reset flag of said next context to be processed.

24. The multithread processor of claim 9, wherein said sequence control, for each of said contexts of said multithread processor which does not correspond to said current context flag, in each case updates said corresponding context parameter set and writes said updated context parameter sets to said program address table.

25. The multithread processor of claim 6, comprising a a selection device receiving said context parameter set of said current context, said context parameter set of said target context of said internal exception and said context parameter set of said target context of said external exception from said switching table, said context parameter set of said current context from said program address table and said next program address from said instruction decoder and, in a manner dependent thereon, generates said next program instruction address and the associated of said squash reset flag of said current context and transmits them to said sequence control.

26. The multithread processor of claim 2, wherein each of said pipeline stages which is arranged downstream of said instruction decoding pipeline stage provides an internal exception upon occurrence of an interrupt.

27. A method for operating a multithread processor for the data processing of threads, each comprising a dedicated context within said multithread processor;

said method comprising the steps of;

receiving at least one of an internal exception of a specific context for updating said context and switching from said context to a target context of said internal exception, or an external exception of a specific context for updating said context and switching from said context to a target context of said external exception;

updating at least one of a context parameter set of said context, a context parameter set of said target context of said internal exception, or a context parameter set of said target context of said external exception; and

setting a switch parameter set for a sequence control of program instructions to be fetched, so that said multithread processor switches between said context and said target context of at least one of said internal or said external exception without restrictions or cycle loss.