Alterable application specific integrated circuit (ASIC)

• US 20060179417A1
• Filed: 04/10/2006
• Published: 08/10/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Tier Logic, Inc.
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 7,345,505 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Claims

1. A three-dimensional semiconductor device, comprising:

a plurality of circuit blocks; and

a configuration circuit to control a portion of the circuit blocks, said configuration circuit further comprising;

a first set of memory elements to store a first instruction; and

a second set of memory elements to store a second instruction; and

a first global control signal to couple or decouple the first set of memory elements from the configuration circuit; and

a second global control signal to couple or decouple the second set of memory elements from the configuration circuits;

wherein, the global control signals select the first or second instruction to control said portion of the circuit blocks.

2. The device of claim 1, wherein the circuit blocks comprises programmable logic elements.

3. The device of claim 1, wherein the configuration circuit is user configurable, and wherein the user configurability is achieved by changing the memory data in said first and second sets of memory elements.

4. The device of claim 1, wherein the circuit blocks comprises capacitive nodes, and wherein the configuration circuit comprises control signals coupled to a portion of the capacitive nodes.

5. The device of claim 4, wherein the control signals are at digital one or at digital zero voltage levels.

6. The device of claim 1, wherein the first or second or both sets of memory elements comprise user configurable Random Access Memory (RAM) elements or mask configured Read Only Memory (ROM) elements.

7. The device of claim 6, wherein the RAM element is selected from one of fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, optical elements, electro-chemical elements and magnetic elements.

8. The device of claim 6, wherein the RAM memory element comprises one or more of:

resistor, diode, capacitor, transistor, thin film device, thin film resistor, thin film capacitor, thin film transistor (TFT).

9. The device of claim 6, wherein the ROM element is comprised of:

a wire connection to a power-bus to provide a logic one data storage; and

a wire connection to a ground-bus to provide a logic zero data storage.

10. The device of claim 1, further comprising interconnects and routing signals to couple the circuit blocks and the configuration circuit.

11. The device of claim 1, further comprising:

K additional sets of memory elements, wherein each of the K additional sets of memory elements store an instruction for the configuration circuit to control said portion of the circuit blocks; and

K additional global control signals, wherein each of the K additional control signals couple or decouples one of the K sets of memory elements from the configuration circuit.

12. A programmable storage unit in an integrated circuit that generates an output coupled to a capacitive node of a programmable circuit, said storage unit comprising:

a first select device coupled to said output; and

a first configuration memory circuit coupled to said first select device; and

a first control signal coupled to said first select device to selectively couple or decouple said first configuration memory circuit from said output; and

a second select device coupled to said output; and

a second configuration memory circuit coupled to said second select device; and

a second control signal coupled to said second select device to selectively couple or decouple said second configuration memory circuit from said output;

wherein, the output value can be switched between the first and second configuration memory bits by activating said first or second control signals respectively.

13. The unit of claim 12, wherein the programmable circuit is programmed by a digital zero or digital one signal level at said output.

14. The unit of claim 12, wherein the programmable circuit is a pass-gate logic circuit further comprising:

a first and a second node; and

a gate electrode coupled to said output, wherein a logic one on the output couples the first node to second node, and a logic zero on the output decouples the first node from said second node.

15. The unit of claim 12, wherein the programmable circuit is an inverter logic circuit comprising:

an inverter input coupled to said storage unit output; and

an inverter output capable of driving a logic state, wherein a logic one on the storage output drives a logic zero state, and a logic zero on the storage output drives a logic one state.

16. The unit of claim 12, wherein the first or second configuration memory circuits comprises memory elements further comprising one of:

fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, Flash cells, Ferro-Electric elements, Electro-Chemical cells, Electro-Magnetic cells, Carbon nano-tubes, Optical elements and Magnetic elements.

17. The unit of claim 12, wherein the first or second or both configuration memory circuits comprises either user configurable Random Access Memory (RAM) elements or mask configured Read Only Memory (ROM) elements.

18. A semiconductor device comprising a circuit block programmable to a plurality of user specifications by a configuration circuit, wherein the configuration circuit comprises:

a first set of memory elements to store a first specification; and

a second set of memory elements to store a second specification; and

one or more control signals to switch between said first or second specification to program the circuit block.

19. The device of claim 18, wherein the circuit block further comprises programmable pass-gate logic elements, wherein the pass-gate is controlled by a control signal generated by the configuration circuit.

20. The device of claim 18, wherein the memory elements further comprises either user configurable Random Access Memory (RAM) elements or mask configured Read Only Memory (ROM) elements.