Circuit board for reducing crosstalk of signals

• US 20060180917A1
• Filed: 02/02/2006
• Published: 08/17/2006
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hoppe, Wolfgang, Djordjevic, Srdjan
• Granted Patent: US 7,375,983 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09518 Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

A circuit board includes a first group of layers located close to a top side of the circuit board, and a second group of layers located close to an underside of the circuit board. Signals which are fed to input and output contact terminals on the top side of the circuit board are passed along at least one of the layers of the group. Signals which are fed to input and output contact terminals on the underside of the circuit board are passed along at least one of the layers of the second group. The contact-making holes for connecting the input and output contact terminals to the layers of the first and second groups are preferably formed as blind contact-making holes.

Claims

1. A circuit board for reducing crosstalk of signals, the circuit board comprising:

a first surface and a second surface;

a plurality of layers aligned with respect to each other in a stacked arrangement between the first surface and the second surface, wherein a first group of the layers is located closer to the first surface than the second surface of the circuit board and a second group of the layers is located closer to the second surface than the first surface of the circuit board;

a semiconductor control component arranged on the first surface of the circuit board;

a pair of first contact terminals arranged on the first surface of the circuit board, wherein one of the first contact terminals is configured to apply a first input signal and the other of the first contact terminals is configured to generate a first output signal;

a pair of second contact terminals arranged on the second surface of the circuit board, wherein one of the second contact terminals is configured to apply a second input signal and the other of the second contact terminals is configured to generate a second output signal;

a pair of first conductor tracks, wherein one of the first conductor tracks is configured to transmit the first input signal from the one of the first contact terminals to the semiconductor control component and the other of the first conductor tracks is configured to transmit the first output signal from the semiconductor control component to the other of the first contact terminals;

a pair of second conductor tracks, wherein one of the second conductor tracks is configured to transmit the second input signal from the one of the second contact terminals to the semiconductor control component and the other of the second conductor tracks is configured to transmit the second output signal from the semiconductor control component to the other of the second contact terminals;

wherein the first conductor tracks run within at least one of the layers of the first group of the layers, and the second conductor tracks run within at least one of the layers of the second group of the layers.

2. The circuit board of claim 1, wherein:

the layers of the first group comprise a first layer and a second layer, the first layer of the first group is located closer to the first surface of the circuit board than the second layer of the first group; and

the layers of the second group comprise a first layer and a second layer, the first layer of the second group is located closer to the second surface of the circuit board than the second layer of the second group; and

at least one of the first conductor tracks runs within the first layer of the first group, and at least one of the second conductor tracks runs within the second layer of the second group.

3. The circuit board of claim 2, further comprising:

a first continuous contact-making hole and a second continuous contact-making hole, wherein each contact-making hole extends from the first surface to the second surface of the circuit board;

wherein at least one of the first conductor tracks runs from the first contact terminals through the first continuous contact-making hole to the first layer of the first group, and at least one of the second conductor tracks runs from the second contact terminals through the second continuous contact-making hole to the first layer of the second group.

4. The circuit board of claim 2, further comprising:

a first blind contact-making hole extending from the first surface of the circuit board to the first layer of the first group; and

a second blind contact-making hole extending from the second surface of the circuit board to the first layer of the second group;

wherein at least one of the first conductor tracks runs from the first contact terminals through the first blind contact-making hole to the first layer of the first group, and at least one of the second conductor tracks runs from the second contact terminals through the second blind contact-making hole to the first layer of the second group.

5. The circuit board of claim 2, wherein:

the one of the first conductor tracks runs within the first layer of the first group;

the other of the first conductor tracks runs within the second layer of the first group;

the one of the second conductor tracks runs within the first layer of the second group; and

the other of the second conductor tracks runs within the second layer of the second group.

6. The circuit board of claim 5, further comprising:

first, second, third and fourth continuous contact-making holes, each continuous contact-making hole extending from the first surface to the second surface of the circuit board;

wherein;

the one of the first conductor tracks runs from the one of the first contact terminals through the first continuous contact-making hole to the first layer of the first group, and the one of the second conductor tracks runs from the one of the second contact terminals through the second continuous contact-making hole to the first layer of the second group; and

the other of the first conductor tracks runs from the other of the first contact terminals through the third continuous contact-making hole to the second layer of the first group, and the other of the second conductor tracks runs from the other of the second contact terminals through the fourth continuous contact-making hole to the second layer of the second group.

7. The circuit board of claim 5, further comprising:

a first blind contact-making hole extending from the first surface of the circuit board to the first layer of the first group;

a second blind contact-making hole extending from the second surface of the circuit board to the first layer of the second group;

a third blind contact-making hole extending from the first surface of the circuit board to the second layer of the first group; and

a fourth blind contact-making hole extending from the second surface of the circuit board to the second layer of the second group;

wherein;

the one of the first conductor tracks runs from the one of the first contact terminals through the first blind contact-making hole to the first layer of the first group, and the one of the second conductor tracks runs from the one of the second contact terminals through the second blind contact-making hole to the first layer of the second group; and

the other of the first conductor tracks runs from the other of the first contact terminals through the third blind contact-making hole to the second layer of the first group, and the other of the second conductor tracks runs from the other of the second contact terminals through the fourth blind contact-making hole to the second layer of the second group.

8. The circuit board of claim 7, further comprising:

a fifth blind contact-making hole extending from one of the layers of the first group to the first surface of the circuit board; and

a fifth continuous contact-making hole extending from the first surface to the second surface of the circuit board;

wherein;

the first conductor tracks run from the one of the layers of the first group through the fifth blind contact-making hole to the semiconductor control component; and

the second conductor tracks run from one of the layers of the second group through the fifth continuous contact-making hole to the semiconductor control component.

9. The circuit board of claim 1, further comprising:

a plurality of semiconductor memory components arranged on the semiconductor board, wherein the semiconductor control component controls read and write accesses to the semiconductor memory components.

10. The circuit board of claim 9, wherein each of the semiconductor memory components includes a memory chip with dynamic random access memory cells.

11. The circuit board of claim 1, wherein the semiconductor control component includes a hub chip.

12. The circuit board of claim 11, wherein the hub chip of the semiconductor control component is located in a ball grid array housing.

13. The circuit board of claim 1, wherein the circuit board is formed as a fully buffered dual in-line memory circuit board.