METHOD AND APPARATUS FOR LOCATING AND TESTING A CHIP

• US 20060181291A1
• Filed: 02/14/2005
• Published: 08/17/2006
• Est. Priority Date: 02/14/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.), Hong Kong University of Science and Technology
• Original Assignee: International Business Machines Corporation
• Inventors: Atwood, Eugene R.
• Granted Patent: US 7,218,128 B2
• Time in Patent Office: Days
• US Class Current: 324/750.250
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 31/2887 involving moving the probe head or the IC under test; docking stations moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392

Abstract

A probe apparatus includes a nest element operable to precisely locate a chip having a plurality of exposed interconnects on a face of the chip to permit conductive connection to the chip through the interconnects. The nest element includes a pocket dimensioned to locate the chip within a tolerance of less than a width of one of the interconnects, and tapered walls extending upwardly and outwardly from the pocket, the tapered walls adapted to guide the chip into the pocket. One or more piezoelectric elements can be attached to or provided within to the nest element to impart vibration to the nest element, causing the chip to be “fluidized” such that the chip is guided into the pocket under the force of gravity or other externally applied force.

Claims

1. A nest element operable to precisely locate a chip having a plurality of interconnects exposed at a face of the chip to permit conductive connection to the chip through said interconnects, comprising:

a pocket dimensioned to locate the chip within a tolerance of less than a width of one of said interconnects;

a plurality of tapered walls extending upwardly and outwardly from said pocket, said tapered walls adapted to receive a chip placed within said nest element and to guide the chip into said pocket under at least one of a force of gravity and an externally applied force; and

one or more vibration inducing devices activatable separately from a process used to place the chip within the nest element to impart a vibratory motion to the nest element to cause the placed chip to be guided along said tapered walls into said pocket.

3. The nest element as claimed in claim 1, wherein said devices include piezoelectric devices.

4. The nest element as claimed in claim 1, wherein said pocket is defined by a plurality of substantially vertical pocket walls, and a plurality of hollowed corners having relaxed radius at junctions of said pocket walls.

5. The nest element as claimed in claim 4, wherein a plurality of edges shared by said substantially vertical pocket walls and said tapered walls have relaxed radius.

6. The nest element as claimed in claim 5, further comprising a plurality of exposed grooves extending outwardly from said hollowed corners between adjacent ones of said tapered walls.

7. The nest element as claimed in claim 1, wherein said nest element includes a structure having an opening defining said pocket, said structure consisting essentially of at least one material selected from the group consisting of a high-temperature polymer, glass, ceramic, and metal.

8. The nest element as claimed in claim 3, further comprising mechanically sprung electrical connectors, said connectors conductively connected to said piezoelectric devices.

9. A probe apparatus including the nest element claimed in claim 1, further comprising:

a probe element having inner contacts facing said interconnects and outer contacts facing away from said interconnects, said interconnects being aligned to the chip-facing contacts when the chip is located by said pocket; and

an interconnect element having wiring traces and a plurality of terminals aligned to said outer contacts to provide conductive interconnection through said probe element to the chip when the chip is located by said pocket.

10. The probe apparatus as claimed in claim 9, wherein said inner contacts of said probe element are shaped to pierce exposed surfaces of said interconnects.

11. The probe apparatus as claimed in claim 9, wherein said pocket is defined by an opening of said nest element, said probe element includes a probe frame aligned to said nest element, and said nest element, said probe frame and said interconnect element including vacuum distribution channels operable to clamp said nest element to said probe element and said probe element to said interconnect element.

12. The probe apparatus as claimed in claim 11, wherein said probe frame and said interconnect element include vacuum ports operable to distribute a vacuum through said interconnect element and said probe element to vacuum distribution channels of said nest element.

13. The probe apparatus as claimed in claim 12, wherein said vacuum ports are adapted to carry a pressurized fluid to said vacuum distribution channels of said nest element to cause said nest element to be released from said probe element.

14. The probe apparatus as claimed in claim 9, further comprising a pressure contactor having a back plate operable to apply a pressure to a rear surface of the chip to establish conductive contact between said interconnects and said inner contacts of said probe.

15. The probe apparatus as claimed in claim 14, wherein said back plate includes at least one vacuum distribution channel for placement adjacent to the rear surface of the chip to apply a vacuum to the rear surface of the chip, and at least one fluid distribution channel for carrying a fluid to the rear surface of the chip to provide said at least one of cooling and heating to the chip, the vacuum distribution channel being operable to scavenge the fluid, the back plate further being operable to eject the chip by maintaining the fluid at a pressure while releasing the vacuum from the rear surface of the chip.

16. The probe apparatus as claimed in claim 14, wherein said back plate is operable to provide at least one of cooling and heating to a rear surface of the chip to control a temperature of the chip.

17. The probe apparatus as claimed in claim 14, further comprising a gimbaling mechanism operable to align a plane defined by said back plate to a plane defined by a rear surface of the chip.

2. (canceled)

18. A probe apparatus, comprising:

a nest element operable to precisely locate a chip having a plurality of exposed interconnects on a face of the chip to permit conductive connection to the chip through said interconnects, the nest element including a pocket dimensioned to locate the chip within a tolerance of less than a width of one of said interconnects, tapered walls extending upwardly and outwardly from said pocket to receive a chip placed within said nest element and to guide the chip into said pocket, and one or more vibration inducing devices activatable separately from a process used to place the chip within the nest element to impart a vibratory motion to the nest element to cause the placed chip to be guided along said tapered walls into said pocket;

a probe element having inner contacts facing said interconnects and outer contacts facing away from said interconnects, the interconnects being aligned to said inner contacts when the chip is located by said pocket; and

an interconnect element having wiring traces and a plurality of terminals aligned to said outer contacts to provide conductive interconnection through said probe element to the chip when the chip is located by said pocket.

19. A method of locating a chip to permit conductive connection to the chip through a plurality of interconnects exposed on a face of the chip, comprising:

placing the chip at least coarsely within a nest element, the nest element including a pocket dimensioned to locate the chip within a tolerance of less than a width of one of the interconnects, the nest element having tapered walls extending upwardly and outwardly from the pocket to receive the chip, the tapered walls adapted to guide the chip into the pocket; and

activating one or more vibration inducing devices separately from actions performed to place the chip within the nest element to impart a vibratory motion to the nest element to cause the placed chip to be guided along the tapered walls into the pocket.

20. A method of testing a chip including the method of locating the chip as claimed in 19, further comprising clamping the nest element to a probe element having conductive contacts aligned to the pocket, clamping the chip to the probe element to establish conductive contact between the interconnects of the chip and the conductive contacts, and flowing currents through the conductive contacts and the interconnects of the chip to test the chip.

21. A method of simultaneously testing a plurality of chips, comprising:

arranging a plurality of probe apparatuses in an array, each probe apparatus including a nest element having a pocket dimensioned to locate one chip within a tolerance of less than a width of one of a plurality of exposed interconnects of the chip, each nest element having tapered walls extending upwardly and outwardly from the pocket and adapted to guide the chip into the pocket, the probe apparatuses further including probe elements having conductive contacts aligned to the pockets;

placing chips with at least coarse alignment into the nest elements of respective ones of the plurality of probe apparatuses;

imparting vibratory motion to the probe apparatuses by actions separate from actions performed to place the chips during said step of placing to guide the chips into the pockets of the probe apparatuses;

clamping the chips to the respective probe elements to establish conductive contact between the interconnects of the chips and the conductive contacts of the probe elements; and

applying voltages and flowing currents simultaneously through the conductive contacts of at least some of the probe apparatuses and the interconnects of at least some of the chips to simultaneously test at least some of the chips.

22. A method as claimed in claim 21, wherein said step of placing chips is performed by feeding out the chips individually from a feed mechanism carried by a robotic placer.

23. A method as claimed in claim 21, further comprising, after said step of applying voltages and flowing currents, collecting the chips into a take-up mechanism carried by a robotic placer.

24. A method as claimed in claim 23, further comprising, after said step of applying voltages and flowing currents, determining that individual ones of the chips do not show good test results and segregating those individual ones of the chips from others of the chips that show good test results.