Adaptive predistortion for a transmit system

• US 20060181345A1
• Filed: 04/10/2006
• Published: 08/17/2006
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Inventors: Saed, Aryan
• Granted Patent: US 7,295,066 B2
• Time in Patent Office: Days
• US Class Current: 330/149
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a signal processing system which includes a predistortion subsystem. The input signal is decomposed and the fragments are then predistorted by the predistortion subsystem by applying a deliberate predistortion to the fragments. The predistorted fragments are then separately processed and recombined to arrive at the system output signal. The predistortion subsystem adaptively adjusts based on characteristics of the system output signal. Also, the predistortion subsystem is equipped with a control system that is state based—the state of the predistortion subsystem is dependent upon the prevailing conditions and, when required, the control system switches the state of the predistortion subsystem. A feedback signal, a replica of the system output signal, is used in updating lookup table entries used to determine the predistortion.

Claims

1-45. -45. (canceled)

46. A preprogrammed control device for use in controlling an adaptive predistortion subsystem, said device being programmed with a predefined set of states, each state having associated with it a predefined set of commands to be executed by said subsystem when said device is in said state, the device comprising:

a processor means for receiving and processing data relating to a status of said subsystem;

first memory means for storing said data;

and second memory means for storing preprogrammed settings for said device, wherein

when said device detects one of a set of specific, predetermined conditions, said device switches from one state to another.

47. A control device according to claim 46 wherein said device controls an update duty cycle for said subsystem, said update duty cycle being determinative of how often said subsystem updates at least one internal lookup table.

50. A control device according to claim 46 wherein said control device switches from one state to another based on input from a distortion monitor which monitors a level of distortion for said subsystem.

48. A control device according to claim 48 wherein said device controls an initialization duty cycle for said subsystem, said initialization duty cycle being determinative of how often said subsystem initializes itself.

49. A control device according to claim 48 wherein said initialization duty cycle is dependent on how often said subsystem updates at least one internal lookup table.

51-60. -60. (canceled)

61. A programmable control device capable of controlling a predistortion subsystem for a transmission system, the programmable control device being programmable with one or more states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem if the programmable control device is in an associated state, the programmable control device comprising:

a processor capable of processing data relating to a status of the predistortion subsystem; and

a memory circuit capable of storing settings for the programmable control device;

wherein, responsive to the data, said processor causes the preprogrammed control device to switch from one state to another based at least in part on the settings of said memory circuit.

62. A programmable control device as claimed in claim 61, said processor being capable of controlling an update duty cycle for the predistortion subsystem, the update duty cycle being determinative of how often the predistortion subsystem updates at least one lookup table.

63. A programmable control device as claimed in claim 61, said processor being capable of controlling an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized.

64. A programmable control device as claimed in claim 61, said processor being capable of controlling an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized, the initialization duty cycle being dependent on how often the predistortion subsystem updates at least one lookup table.

65. A programmable control device as claimed in claim 61, said processor being capable of controlling the programmable control device to switch from one state to another based at least in part on input from a distortion monitor that monitors a level of distortion for the predistortion subsystem.

66. A programmable control device as claimed in claim 61, the one or more states comprising one or more of a reset state, a pause state, a hold state, a warm up state, a standby state, an update state, a full initialization state, a re-initialization state, or a cool down state, or combinations thereof.

67. A programmable control device as claimed in claim 61, the one or more states comprising one or more of a reset state, a measure state, a freeze state, a no monitor state, or a monitor state, or combinations thereof.

68. An article of manufacture, comprising:

instructions stored thereon, if executed, capable of causing a programmable control device to control a predistortion subsystem for a transmission system, the programmable control device being programmed with one or more states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem if the programmable control device is in an associated state, by;

processing data relating to a status of the predistortion subsystem; and

storing settings for the programmable control device;

wherein, responsive to the data, the preprogrammed control device switches from one state to another based at least in part on the stored settings.

69. An article of manufacture as claimed in claim 68, wherein the instructions, if executed, further being capable of causing the programmable control device to control a predistortion subsystem for a transmission system, by:

controlling an update duty cycle for the predistortion subsystem, the update duty cycle being determinative of how often the predistortion subsystem updates at least one lookup table.

70. An article of manufacture as claimed in claim 68, wherein the instructions, if executed, further being capable of causing the programmable control device to control a predistortion subsystem for a transmission system, by:

controlling an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized.

71. An article of manufacture as claimed in claim 68, wherein the instructions, if executed, further being capable of causing the programmable control device to control a predistortion subsystem for a transmission system, by:

controlling an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized, the initialization duty cycle being dependent on how often the predistortion subsystem updates at least one lookup table.

72. An article of manufacture as claimed in claim 68, wherein the instructions, if executed, further being capable of causing the programmable control device to control a predistortion subsystem for a transmission system, by:

causing the programmable control device to switch from one state to another based at least in part on input from a distortion monitor that monitors a level of distortion for the predistortion subsystem.

73. An article of manufacture as claimed in claim 68, wherein the one or more states comprise one or more of the following:

a reset state, a pause state, a hold state, a warm up state, a standby state, an update state, a full initialization state, a re-initialization state, or a cool down state, or combinations thereof.

74. An article of manufacture as claimed in claim 68, wherein the one or more states comprise one or more of the following:

a reset state, a measure state, a freeze state, a no monitor state, or a monitor state, or combinations thereof.

75. An application specific integrated circuit capable of controlling a predistortion subsystem of a transmission system, the application specific integrated circuit being programmable with one or more states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem if the application specific integrated circuit is in an associated state, the application specific integrated circuit comprising:

a processor capable of processing data relating to a status of the predistortion subsystem; and

a memory circuit capable of storing settings for the application specific integrated circuit;

wherein, responsive to the data, the processor causes the application specific integrated circuit to switch from one state to another based at least in part on the settings of said memory circuit.

76. An application specific integrated circuit as claimed in claim 75, wherein said processor controls an update duty cycle for the predistortion subsystem, the update duty cycle being determinative of how often the predistortion subsystem updates at least one lookup table.

77. An application specific integrated circuit as claimed in claim 75, wherein said processor controls an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized.

78. An application specific integrated circuit as claimed in claim 75, wherein said processor controls an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized, the initialization duty cycle being dependent on how often the predistortion subsystem updates at least one lookup table.

79. An application specific integrated circuit as claimed in claim 75, wherein said processor causes the application specific integrated circuit to switch from one state to another based at least in part on input from a distortion monitor that monitors a level of distortion for the predistortion subsystem.

80. An application specific integrated circuit as claimed in claim 75, wherein the one or more states comprise one or more of the following:

a reset state, a pause state, a hold state, a warm up state, a standby state, an update state, a full initialization state, a re-initialization state, or a cool down state, or combinations thereof.

81. An application specific integrated circuit as claimed in claim 75, wherein the one or more states comprise one or more of the following:

a reset state, a measure state, a freeze state, a no monitor state, or a monitor state, or combinations thereof.

82. A combinational logic circuit capable of controlling a predistortion subsystem of a transmission system, the combinational logic circuit being programmable with one or more states, one or more of the states being associated with one or more commands to be executed by the predistortion subsystem if the combinational logic circuit is in an associated state, the combinational logic circuit comprising:

a first logic circuit capable of processing data relating to a status of the predistortion subsystem; and

a second logic circuit capable of storing settings for the combinational logic circuit;

wherein, responsive to the data, the first logic circuit causes the combinational logic circuit to switch from one state to another based at least in part on the settings of said second logic circuit.

83. A combinational logic circuit as claimed in claim 82, wherein said first logic circuit controls an update duty cycle for the predistortion subsystem, the update duty cycle being determinative of how often the predistortion subsystem updates at least one lookup table.

84. A combinational logic circuit as claimed in claim 82, wherein said first logic circuit controls an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized.

85. A combinational logic circuit as claimed in claim 82, wherein said first logic circuit controls an initialization duty cycle for the predistortion subsystem, the initialization duty cycle being determinative of how often the predistortion subsystem is initialized, the initialization duty cycle being dependent on how often the predistortion subsystem updates at least one lookup table.

86. A combinational logic circuit as claimed in claim 82, wherein said first logic circuit causes the application specific integrated circuit to switch from one state to another based at least in part on input from a distortion monitor that monitors a level of distortion for the predistortion subsystem.

87. A combinational logic circuit as claimed in claim 82, wherein the one or more states comprise one or more of the following:

a reset state, a pause state, a hold state, a warm up state, a standby state, an update state, a full initialization state, a re-initialization state, or a cool down state, or combinations thereof.

88. A combinational logic circuit as claimed in claim 82, wherein the one or more states comprise one or more of the following:

a reset state, a measure state, a freeze state, a no monitor state, or a monitor state, or combinations thereof.