Semiconductor memory device for low voltage
First Claim
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1. A semiconductor memory device, comprising:
- a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor; and
a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells.
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Abstract
A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.
418 Citations
92 Claims
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1. A semiconductor memory device, comprising:
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a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor; and
a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor memory device, comprising:
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a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor, and a plurality of bit line pairs, wherein the first cell array provides a data signal stored in a unit cell selected from the unit cells to a first bit line pair selected from the bit line pairs, the first bit line pair containing a first bit line and a first bit line bar;
a bit line sense amplifier for sensing and amplifying a voltage difference between the first bit line and the first bit line bar after the data signal is provided to the first bit line pair;
a first reference cell block for transmitting a reference signal to the first bit line bar when the data signal is loaded on the first bit line and for transmitting the reference signal to the first bit line when the data signal is loaded on the first bit line bar; and
a first precharge block for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period without supplying a precharge voltage to the first bit line pair, wherein the first bit line and the first bit line bar are in a floating state during the precharge period. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A method for driving a semiconductor memory device including a plurality of unit cells and a plurality of bit line pairs, comprising:
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turning on a PMOS transistor included in a unit cell selected from the unit cells;
transmitting a data signal stored in the unit cell to a bit line in a corresponding bit line pair; and
sensing and amplifying a voltage difference between the bit line and a bit line bar of the corresponding bit line pair based on a first low voltage which is lower than a ground voltage. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
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55. A method for driving a semiconductor memory device having a folded bit line structure and including a bit line sense amplifier, a first cell array and a second cell array sharing the bit line sense amplifier with the first cell array, comprising:
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connecting a first bit line pair configured in the first cell array to the bit line sense amplifier and disconnecting a second bit line pair configured in the second cell array from the bit line sense amplifier;
activating a PMOS transistor of a unit cell selected from a plurality of unit cells configured in the first cell array to thereby transmit a data signal stored in the unit cell to a first bit line of the first bit line pair, wherein each unit cell has a PMOS transistor and a capacitor;
transmitting a reference signal to a first bit line bar of the first bit line pair; and
sensing and amplifying a voltage difference between the first bit line and the first bit line bar based on a power supply voltage and a first low voltage lower than a ground voltage. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69)
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70. A semiconductor memory device, comprising:
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a first cell array including a plurality of unit cells each of which has a PMOS transistor and a capacitor and transmitting a first data signal stored in a unit cell selected from the plurality of unit cells to a first bit line;
a second cell array including a plurality of unit cells each of which has a PMOS transistor and a capacitor and transmitting a second data signal stored in a unit cell selected from the plurality of the unit cells to a second bit line;
a bit line sense amplifier for sensing and amplifying a voltage difference between the first bit line and the second bit line;
a reference cell block for transmitting a reference signal to the second bit line when the first data signal is loaded on the first bit line and transmitting the reference signal to the first bit line when the second data signal is loaded on the second bit line; and
a precharge block for equalizing the first bit line and the second bit line without supplying the first and the second bit lines with a precharge voltage during a precharge period. - View Dependent Claims (71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92)
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Specification