Erase verify for non-volatile memory

• US 20060181930A1
• Filed: 04/10/2006
• Published: 08/17/2006
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Granted Patent: US 7,196,934 B2
• Time in Patent Office: Days
• US Class Current: 365/185.230
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

Claims

1. A non-volatile memory comprising:

an array of non-volatile memory cells arranged in a row and column format such that the columns comprise bit lines including a selected bit line having a bit line current; and

a plurality of comparators for generating indication signals in response to a comparison of a voltage that is representative of the bit line current with a plurality of reference voltages each coupled to a comparator, each reference voltage indicating a different limit of an erase level window, each comparator generating an indication of one of under-erasure, erasure, or over-erasure in response to the comparison.

2. The non-volatile memory of claim 1 wherein the erase level window indicates a voltage level.

3. The non-volatile memory of claim 1 wherein the indication signals include a “

00”

for under-erasure, a “

10”

for erasure, and a “

11”

for over-erasure.

4. The non-volatile memory of claim 1 wherein the memory cells comprise a plurality of floating gate memory cells.

5. The non-volatile memory of claim 1 wherein the indication signals are logical indications.

6. The non-volatile memory of claim 1 wherein the erase level window indicates a current level.

7. The non-volatile memory of claim 1 wherein the plurality of comparators comprise:

a first comparator with a reference input coupled to receive a first reference voltage of the plurality of reference voltages, and a second input coupled to the selected bit line; and

a second comparator with a reference input coupled to receive a second reference voltage of the plurality of reference voltages, and a second input coupled to the selected bit line.

8. A non-volatile memory comprising:

an array of flash memory cells arranged in a row and column format such that the columns comprise bit lines including a selected bit line having a bit line current and the rows comprise word lines; and

a plurality of comparators for generating indication signals in response to a comparison of a voltage that is representative of the bit line current with a plurality of reference voltages each coupled to a comparator, each reference voltage indicating a different limit of an erase level window, each comparator generating an indication of one of under-erasure, erasure, or over-erasure in response to the comparison.

9. The non-volatile memory of claim 8 wherein the plurality of comparators comprise a first comparator that compares the bit line current to a lower limit reference current and a second comparator that compares the bit line current to an upper limit reference current.

10. The non-volatile memory of claim 8 wherein a bit line current that is less than an upper limit reference current and greater than a lower limit reference current is a current indicating erasure.

11. The non-volatile memory of claim 8 wherein the array of flash memory cells are floating gate memory cells.

12. The non-volatile memory of claim 8 wherein the indication signals are logical indication signals that include a logical “

00”

for under-erasure, a logical “

10”

for erasure, and a logical “

11”

for over-erasure.

13. A memory comprising:

an array of memory cells arranged in a row and column format such that the columns comprise bit lines including a selected bit line having a bit line current and the rows comprise word lines; and

a plurality of comparators for generating indication signals in response to a comparison of a voltage that is representative of the bit line current with a plurality of reference voltages each coupled to a comparator, each reference voltage indicating a different limit of an erase level window, each comparator generating an indication of one of under-erasure, erasure, or over-erasure in response to the comparison.

14. The memory of claim 13 wherein the plurality of comparators comprise:

a first comparator with a reference input coupled to receive a first reference voltage of the plurality of reference voltages for comparison with a second input coupled to the selected bit line; and

a second comparator with a reference input coupled to receive a second reference voltage of the plurality of reference voltages for comparison with a second input coupled to the selected bit line.

15. The memory of claim 13 wherein the erase level window indicates a current level of the selected bit line.

16. The memory of claim 13 wherein the erase level window indicates a voltage level of the selected bit line.