Field effect device having a channel of nanofabric and methods of making same

• US 20060183278A1
• Filed: 01/13/2006
• Published: 08/17/2006
• Est. Priority Date: 01/14/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Rueckes, Thomas, Guo, Frank, Meinhold, Mitchell, Konsek, Steven L.
• Granted Patent: US 8,362,525 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Abstract

Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which the nanotubes of the channel region are substantially all of the same semiconducting type of nanotubes. At least one gate is formed in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region. Forming a channel region includes forming a fabric of nanotubes in which the fabric has both semiconducting and metallic nanotubes and the fabric is processed to remove substantially all of the metallic nanotubes.

Claims

1. A method of making a nanotube field effect transistor, comprising:

providing a substrate;

forming a drain region and a source region in spaced relation relative to each other;

forming a channel region from a fabric of nanotubes, wherein the nanotubes of the channel region are substantially all of the same semiconducting type of nanotubes;

forming at least one gate in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region.

2. The method of claim 1 wherein forming a channel region includes forming a fabric of nanotubes in which the fabric has both semiconducting and metallic nanotubes and the fabric is processed to remove substantially all of the metallic nanotubes.

3. The method of claim 2 wherein the fabric is processed by subjecting it to electrical stimulation so as to fail substantially all of the metallic nanotubes.

4. The method of claim 3 wherein the fabric is electrically biased so as to turn off the conductivity of the semiconducting nanotubes before subjecting the fabric to electrical stimulation to fail the metallic nanotubes.

5. The method of claim 3 wherein the fabric is formed to be a suspended fabric with a gap on at least one side of the fabric to facilitate the failing of the metallic nanotubes.

6. The method of claim 3 wherein the fabric is formed to be a partially suspended fabric with a gap on at least one side of the fabric to facilitate the failing of the metallic nanotubes.

7. The method of claim 1 wherein the field effect transistor is formed to have a front gate and back gate, and wherein the back gate may be used to bias the transistor to translate a current voltage relationship of the transistor to a desired range.

8. The method of claim 1 wherein the channel region is formed by defining the shape of the channel region in a fabric of nanotubes and removing nanotubes from the fabric to result in the formation of the channel region.

9. The method of claim 1 wherein the nanotubes of the channel region are substantially all of the P-type semiconducting nanotubes.

10. The method of claim 1 wherein the nanotubes of the channel region are processed to be substantially all ambipolar semiconducting nanotubes.

11. The method of claim 10 wherein the nanotubes of the channel region are subjected to a desorption process to make the nanotubes of the channel region substantially all ambipolar semiconducting nanotubes.

12. The method of claim 10 wherein the nanotubes of the channel region are processed to be substantially all N-type semiconducting nanotubes.

13. The method of claim 3 wherein the substrate is an active substrate including circuitry therein that may be used to electrically stimulate and fail the metallic nanotubes.

14. The method of claim 13 wherein the circuitry to electrically stimulate and fail the metallic nanotubes operates before completion of the formation the at least one gate.

15. The method of claim 3 wherein an off-chip tester is used to electrically stimulate and fail the metallic nanotubes.

16. The method of claim 3 wherein a large plurality of field effect transistors are made on the same substrate and wherein the substrate is divided to iteratively process the field effect transistors on the substrate to simultaneously electrically stimulate a subset plurality of the channel regions to fail the metallic nanotubes therein.

17. The method of claim 1 wherein the nanotubes are carbon nanotubes.

24. The nanotube logic circuit of claim 1 wherein the first nanotube field effect transistor is connected as a pull-up device and has P-type semiconductive channel region and the second nanotube field effect transistor is connected as a pull-down device and has an ambipolar or N-type channel region.

18. A nanotube field effect transistor comprising:

a drain region and a source region in spaced relation relative to each other;

a channel region connecting the source and drain regions formed of a fabric of nanotubes all of the same semiconducting type of nanotubes;

at least one gate in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region.

19. The nanotube field effect transistor of claim 18 wherein the nanotubes of the channel region are P-type.

20. The nanotube field effect transistor of claim 18 where the nanotubes of the channel region are ambipolar.

21. The nanotube field effect transistor of claim 18 where the nanotubes of the channel region are N-type.

22. The nanotube field effect transistor of claim 18 including a front gate and a back gate in proximity of the channel region, wherein the back gate may be used to bias the transistor to translate a current voltage relationship of the transistor to a desired range and the front gate may be used to modulate the conductivity of the channel region.

23. A nanotube logic circuit, comprising:

at least a first nanotube field effect transistor and a second nanotube field effect transistor interconnected so as to form a logic circuit, each nanotube field effect transistor having

a drain region and a source region in spaced relation relative to each other;

a channel region connecting the source and drain regions formed of a fabric of nanotubes all of the same semiconducting type of nanotubes;

at least one gate in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region;

wherein the channel region of the first nanotube field effect transistor is comprised of a first type of semiconducting nanotube and the channel region of the second nanotube field effect transistor is comprised of a second type of semiconducting nanotube, different than the first type.