Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates

• US 20060183331A1
• Filed: 03/30/2006
• Published: 08/17/2006
• Est. Priority Date: 03/12/2002
• Status: Abandoned Application

• Current Assignee: James J. Hofmann
• Original Assignee: James J. Hofmann
• Inventors: Hofmann, James J.
• Application Number:
  US11/395,476
• Publication Number:
  US 20060183331A1
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: G03F 9/00 Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically G03F7/22 takes precedence; preparation of photographic masks G03F1/00; within photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76817 using printing or stamping techniques
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: Y10S 438/951 : Lift-off

Abstract

The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The mold is then removed from the low-k dielectric material. The invention also includes a method of forming a mold; and includes a mold configured to pattern a mass over a semiconductor substrate during contact lithography of the mass.

Claims

1-44. -44. (canceled)

45. A method for aligning a semiconductor fabrication mold and a semiconductor substrate comprising:

providing a semiconductor fabrication mold having a first alignment article associated therewith;

providing a semiconductor substrate having a second alignment article associated therewith, the semiconductor substrate having a non-photoresist material thereover; and

aligning the first alignment article of the semiconductor fabrication mold relative to the second alignment article of the semiconductor substrate, the non-photoresist material being between the mold and the substrate during the aligning.

46. The method of claim 45 wherein the first article comprises a pin and the second article comprises a receptacle, the aligning comprising mating the pin with the receptacle.

47. The method of claim 45 further comprising utilizing the mold to form a pattern in the material.

48. The method of claim 45 further comprising, after aligning the first and second alignment articles with one another, pressing the mold relative to the material to form a reverse image of at least a portion of the pattern of the mold within the material.

49. The method of claim 45 wherein one of the first and second alignment articles is a pin and the other of the first and second alignment articles is a receptacle;

and wherein the aligning comprises mating the pin within the receptacle.

50. The method of claim 45 wherein:

the second alignment article is a first optical pattern, the first optical pattern being supported by the semiconductor substrate;

the mold comprises a substantially transparent portion and a second optical pattern within the substantially transparent portion; and

the aligning comprises aligning the first and second optical patterns relative to one another.

51. A method of patterning a dielectric material,comprising:

providing a substrate having a dielectric material thereover, the substrate having an optical alignment pattern supported thereby;

providing a mold having a first topographical pattern, the mold comprising a region through which the optical alignment pattern can be viewed during an alignment of the mold and substrate relative to one another;

aligning the mold and substrate relative to one another;

after the aligning, utilizing the mold to press a second topographical pattern in the dielectric material, the second topographical pattern being substantially complementary to the first topographical pattern; and

after utilizing the mold to press the second topographical pattern, removing the mold from over the dielectric material.

52. The method of claim 51 wherein the dielectric material comprises a low-k dielectric material.

53. The method of claim 51 wherein the mold comprises a siloxane.

54. The method of claim 51 wherein the second topographical pattern comprises shallow trenches within the dielectric material and deep openings through the dielectric material.