System and method for managing mirrored memory transactions and error recovery

• US 20060184846A1
• Filed: 02/03/2005
• Published: 08/17/2006
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hillier, Philip Rogers III, McGlone, Elizabeth A., Kirscht, Joseph Allen
• Granted Patent: US 7,328,315 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Abstract

In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Claims

1. In a data processing system having a memory control device including at least two mirrored memory ports, a method for processing read requests comprising:

receiving a read request on a system interconnect;

issuing the received read request only to a specified one of the at least two mirrored memory ports; and

responsive to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, issuing the received read request to an alternate of the at least two mirrored memory ports.

2. The method of claim 1, wherein said detecting an unrecoverable error comprises detecting an error in the data returned responsive to the read request issued to the primary mirrored memory port.

3. The method of claim 2, wherein said memory control device includes a central data buffer for storing data returned from read requests, said method further comprising marking the returned data as invalid such that the returned data is not written to the central data buffer.

4. The method of claim 1, further comprising marking the read request issued to the secondary mirrored memory port as a failover read request.

5. The method of claim 4, further comprising, responsive to detecting an unrecoverable error resulting from the read request issued to the secondary mirrored memory port, commencing a machine check of memory devices coupled to the memory control device.

6. The method of claim 1, further comprising selecting the primary mirrored memory port to unilaterally process one or more read requests.

7. The method of claim 6, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises selecting among the at least two mirrored memory ports in an alternating manner to select the primary mirrored memory port to issue a given read request.

8. The method of claim 6, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

monitoring a read request queue level for each of the at least two mirrored memory ports;

responsive to determining that the read request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, asserting a port available signal corresponding to the given memory port;

responsive to determining that the read request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, asserting a port busy signal corresponding to the one or more other mirrored memory ports; and

prioritizing the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having port available asserted are selected as the primary mirrored memory port prior to ports having port busy asserted.

9. The method of claim 6, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

comparing read request queue levels of the at least two mirrored memory ports; and

issuing read requests to the mirrored memory port having the lowest read request queue level.

10. The method of claim 6, wherein said received read request is associated with a specified memory device identifier, said selecting the primary mirrored memory port to unilaterally process one or more read requests comprising:

comparing bank the memory device identifier specified by the read request with memory device identifiers specified by currently queued read requests for the other at least two mirrored memory ports; and

issuing the received read request to a mirrored port having a different memory device identifier that that specified by the read request.

11. The method of claim 6, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

monitoring a write request queue level for each of the at least two mirrored memory ports;

responsive to determining that the write request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, asserting a non-write busy signal corresponding to the given memory port;

responsive to determining that the write request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, asserting a write busy signal corresponding to the one or more other mirrored memory ports; and

prioritizing the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having non-write busy asserted are selected as the primary mirrored memory port prior to ports having write busy asserted.

12. In a data processing system having a memory control device including at least two mirrored memory ports, a system for processing read requests comprising:

means for receiving a read request on a system interconnect;

means for issuing the received read request only to a specified one of the at least two mirrored memory ports; and

means responsive to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, for issuing the received read request to an alternate of the at least two mirrored memory ports.

13. The system of claim 12, wherein said means for detecting an unrecoverable error comprises means for detecting an error in the data returned responsive to the read request issued to the primary mirrored memory port.

14. The system of claim 12, further comprising logic for marking the read request issued to the secondary mirrored memory port as a failover read request.

15. The system of claim 14, further comprising, logic responsive to detecting an unrecoverable error resulting from the read request issued to the secondary mirrored memory port, that commences a machine check of memory devices coupled to the memory control device.

16. The system of claim 12, further comprising logic that selects the primary mirrored memory port to unilaterally process one or more read requests.

17. The system of claim 16, wherein said logic selecting the primary mirrored memory port to unilaterally process one or more read requests comprises logic that selects among the at least two mirrored memory ports in an alternating manner to select the primary mirrored memory port to issue a given read request.

18. The system of claim 16, wherein said logic selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

means for monitoring a read request queue level for each of the at least two mirrored memory ports;

logic means responsive to determining that the read request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, that asserts a port available signal corresponding to the given memory port;

logic means responsive to determining that the read request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, that asserts a port busy signal corresponding to the one or more other mirrored memory ports; and

logic that prioritizes the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having port available asserted are selected as the primary mirrored memory port prior to ports having port busy asserted.

19. The system of claim 16, wherein said logic selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

logic that compares read request queue levels of the at least two mirrored memory ports; and

circuitry that issues read requests to the mirrored memory port having the lowest read request queue level.

20. The system of claim 16, wherein said received read request is associated with a specified memory device identifier, said logic selecting the primary mirrored memory port to unilaterally process one or more read requests comprising:

logic comparing bank the memory device identifier specified by the read request with memory device identifiers specified by currently queued read requests for the other at least two mirrored memory ports; and

circuitry issuing the received read request to a mirrored port having a different memory device identifier that that specified by the read request.

21. The system of claim 16, wherein said logic selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

logic that monitors a write request queue level for each of the at least two mirrored memory ports;

logic responsive to determining that the write request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, that asserts a non-write busy signal corresponding to the given memory port;

logic responsive to determining that the write request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, that asserts a write busy signal corresponding to the one or more other mirrored memory ports; and

logic that prioritizes the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having non-write busy asserted are selected as the primary mirrored memory port prior to ports having write busy asserted.

22. A computer-readable medium having encoding thereon computer-executable instructions for processing read requests in a data processing system having a memory control device including at least two mirrored memory ports, said computer-executable instructions performing a method comprising:

receiving a read request on a system interconnect;

issuing the received read request only to a specified one of the at least two mirrored memory ports; and

responsive to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, issuing the received read request to an alternate of the at least two mirrored memory ports.

23. The computer-readable medium of claim 22, wherein said detecting an unrecoverable error comprises detecting an error in the data returned responsive to the read request issued to the primary mirrored memory port.

24. The computer-readable medium of claim 23, wherein said memory control device includes a central data buffer for storing data returned from read requests, said method further comprising marking the returned data as invalid such that the returned data is not written to the central data buffer.

25. The computer-readable medium of claim 22, wherein said method further comprises marking the read request issued to the secondary mirrored memory port as a failover read request.

26. The computer-readable medium of claim 25, wherein said method further comprises, responsive to detecting an unrecoverable error resulting from the read request issued to the secondary mirrored memory port, commencing a machine check of memory devices coupled to the memory control device.

27. The computer-readable medium of claim 22, wherein said method further comprises selecting the primary mirrored memory port to unilaterally process one or more read requests.

28. The computer-readable medium of claim 27, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises selecting among the at least two mirrored memory ports in an alternating manner to select the primary mirrored memory port to issue a given read request.

29. The computer-readable medium of claim 27, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

monitoring a read request queue level for each of the at least two mirrored memory ports;

responsive to determining that the read request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, asserting a port available signal corresponding to the given memory port;

responsive to determining that the read request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, asserting a port busy signal corresponding to the one or more other mirrored memory ports; and

prioritizing the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having port available asserted are selected as the primary mirrored memory port prior to ports having port busy asserted.

30. The computer-readable medium of claim 27, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

comparing read request queue levels of the at least two mirrored memory ports; and

issuing read requests to the mirrored memory port having the lowest read request queue level.

31. The computer-readable medium of claim 27, wherein said received read request is associated with a specified memory device identifier, said selecting the primary mirrored memory port to unilaterally process one or more read requests comprising:

comparing bank the memory device identifier specified by the read request with memory device identifiers specified by currently queued read requests for the other at least two mirrored memory ports; and

issuing the received read request to a mirrored port having a different memory device identifier that that specified by the read request.

32. The computer-readable medium of claim 27, wherein said selecting the primary mirrored memory port to unilaterally process one or more read requests comprises:

monitoring a write request queue level for each of the at least two mirrored memory ports;

responsive to determining that the write request queue level for a given one or the at least two mirrored memory ports is less than a specified threshold level, asserting a non-write busy signal corresponding to the given memory port;

responsive to determining that the write request queue level for one or more other of the at least two mirrored memory ports is greater than or equal to a specified threshold level, asserting a write busy signal corresponding to the one or more other mirrored memory ports; and

prioritizing the mirrored memory ports for being selected as the primary mirrored memory port such that memory ports having non-write busy asserted are selected as the primary mirrored memory port prior to ports having write busy asserted.