Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device

• US 20060184863A1
• Filed: 04/03/2006
• Published: 08/17/2006
• Est. Priority Date: 10/17/2001
• Status: Active Grant

• Current Assignee: Hyung-Joon Kwon, Il-Man Bae
• Original Assignee: Hyung-Joon Kwon, Il-Man Bae
• Inventors: Bae, Il-man, Kwon, Hyung-joon
• Granted Patent: US 7,586,808 B2
• Time in Patent Office: Days
• US Class Current: 714/784
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/1555 Pipelined decoder implementations
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Claims

1. A random access memory (RAM) which data is written to and read from at the same time during decoding of one frame of data, the RAM comprising:

a plurality of banks,

wherein when a first bank is selected from the plurality of banks in response to a first control signal, predetermined data is written to the first bank,

when a second bank is selected from the plurality of banks in response to a second control signal, the data stored in the second bank is output, and

the first and second banks are selected with a predetermined offset per frame of data.

2. The RAM of claim 1, wherein the RAM is SDRAM or DRAM.

3. The RAM of claim 1, wherein the size of each bank is determined to be sufficient to store one frame of data.

4. The RAM of claim 1, wherein the writing/reading of data is performed via an input/output pin.

5. The RAM of claim 1, wherein the first control signal comprises a first bank selection signal for selecting the first bank and a write command signal for commanding writing of the predetermined data to the first bank, and

the second control signal comprises a second bank selection signal for selecting the second bank and a read command signal for commanding reading of data from the second bank.