DMOS device having a trenched bus structure

• US 20060186465A1
• Filed: 01/10/2006
• Published: 08/24/2006
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chuang, Chiao-Shun, Hsieh, Hsin-Huang, Tseng, Mao-Song, Chang, Chien-Ping
• Granted Patent: US 7,265,024 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Claims

1-15. -15. (canceled)

16. A method of forming a trenched DMOS device, the method comprising:

providing an N+ silicon substrate with an N epitaxial layer thereon, and a P substrate in the N epitaxial layer extending to a top surface thereof;

forming in a device region a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof, and in a bus region a field oxide layer on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;

forming a gate oxide layer in the DMOS trenches and extending to cover the top surface of the P substrate adjacent the DMOS trenches, and a gate oxide layer in the bus trench and extending to cover the top surface of the P substrate adjacent the bus trench;

forming a plurality of polysilicon gates in the DMOS trenches, and a polysilicon bus in the bus trench, the polysilicon bus having a top surface disposed at a lower level than the top surface of the field oxide layer;

forming a plurality of N+ source regions in the P substrate adjacent the DMOS trenches;

forming a plurality of P+ diffused regions in the P substrate, each of the P+ diffused regions being interposed between two of the N+ source regions;

forming a first isolation layer over the P substrate to cover the polysilicon gates, and a second isolation layer to cover the field oxide layer, the second isolation layer having an opening to expose the polysilicon bus; and

forming a source metal contact layer on the first isolation layer, and a metal line atop the polysilicon bus, the source metal contact layer connecting to the N+ source regions and the P+ diffused regions.

17. The method of claim 16, wherein the P substrate of the device region and the P substrate of the bus region are formed by ion implantation simultaneously.

18. The method of claim 16, wherein the gate oxide layer of the device region and the gate oxide layer of the bus region are formed simultaneously.

19. The method of claim 16, wherein the polysilicon gate and the polysilicon bus are formed by depositing a polysilicon layer in the DMOS trenches and the bus trench and using the gate oxide layers as etch stop layers to etch the polysilicon layer.

20. The method of claim 16, wherein the plurality of N+ source regions are formed in the P substrate on opposite sides of each of the DMOS trenches.

21. A method of forming a semiconductor device set which comprises at least two types of devices, each of the two types of devices having a trench feature, the method comprising:

forming, in the first device, a gate oxide in the trench feature, a polysilicon layer on the gate oxide in the trench features, a first isolation layer on the polysilicon layer and having an opening, and a metal layer on the first isolation layer and filling the opening of the first isolation layer; and

forming, in the second device, a dielectric layer adjacent an opening at a top of the trench feature on opposite sides of the trench feature which extends downward from a top surface of the dielectric layer, a gate oxide in the trench feature and over the dielectric layer, a polysilicon layer on the gate oxide in the trench feature including a space below the top of the trench feature between the top surface of the dielectric layer and an upper surface of the polysilicon layer with the dielectric layer disposed on opposite sides thereof, a second isolation layer on the dielectric layer and having an opening to expose the polysilicon layer, and a metal layer on the exposed polysilicon layer.

22. The method of claim 21, wherein the at least two types of devices are formed on a silicon substrate.

23. The method of claim 22, wherein the silicon substrate has an epitaxial layer formed thereon.

24. The method of claim 23, wherein the epitaxial layer has a P substrate thereon.

25. The method of claim 24, wherein each trench feature extends through the P substrate to an area below a top surface of the epitaxial layer.

26. The method of claim 24, wherein a plurality of N source regions and a plurality of P regions are formed in the P substrate.

27. The method of claim 26, wherein at least two of the N source regions formed in the P substrate are disposed adjacent to and on opposites sides of one of the first devices, and wherein at least one of the P regions formed in the P substrate is disposed between two adjacent N source regions.

28. The method of claim 23, wherein the epitaxial layer is an N epitaxial layer.

29. The method of claim 22, wherein the silicon substrate is an N substrate.

30. The method of claim 21 wherein the dielectric layer in the second device comprises a field oxide layer.

31. The method of claim 21 wherein the gate oxide in the trench feature of the first device and the gate oxide in the trench feature of the second device are formed simultaneously.

32. The method of claim 21 wherein the polysilicon layer on the gate oxide of the first device and the polysilicon layer on the gate oxide of the second device are formed simultaneously.

33. The method of claim 21 wherein the first isolation layer without the opening and the second isolation without the opening are formed simultaneously.

34. The method of claim 33 wherein the opening in the first isolation layer and the opening in the second isolation layer are formed simultaneously.

35. The method of claim 21 wherein the metal layer on the first isolation layer of the first device and the metal layer on the exposed polysilicon layer of the second device are formed simultaneously.