Field effect transistor with narrow bandgap source and drain regions and method of fabrication

• US 20060186484A1
• Filed: 02/23/2005
• Published: 08/24/2006
• Est. Priority Date: 02/23/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Datta, Suman, Metz, Matthew
• Granted Patent: US 7,518,196 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Claims

1. A transistor comprising:

a gate electrode formed on a gate dielectric layer formed on a silicon layer; and

a pair of source/drain regions formed on opposite sides of said gate electrode, said pair of source/drain regions comprising a narrow bandgap semiconductor film.

2. The transistor of claim 1 wherein said narrow bandgap semiconductor film has energy bandgap of less than 0.7 eV.

3. The transistor of claim 2 wherein said narrow bandgap semiconductor film is selected from the group consisting of indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs(x>

50%)) and indium phosphide (InP).

4. The transistor of claim 1 wherein said narrow bandgap semiconductor film has a bulk mobility between 10,000 to 80,000.

5. The transistor of claim 1 wherein said narrow bandgap semiconductor film has a melting point of less than 550°

C.

6. The transistor of claim 1 further comprising a pair of sidewall spacers formed along opposite sides of said gate electrode, and wherein said narrow bandgap semiconductor film is formed adjacent to said sidewalls spacers and above the top surface of said gate dielectric layer.

7. The transistor of claim 1 wherein said silicon layer is a portion of a monocrystalline silicon substrate.

8. The transistor of claim 1 wherein said silicon layer is an epitaxial silicon film formed on a buried oxide layer formed on a monocrystalline silicon substrate.

9. The transistor of claim 1 wherein said pair of source/drain regions have bottom surface in contact with said silicon layer.

10. The transistor of claim 1 wherein said narrow bandgap semiconductor film is doped to an n type conductivity.

11. The transistor claim 1 wherein said narrow bandgap semiconductor film is doped with a dopant selected from the group consisting of Te or Si or S.

12. The semiconductor device of claim 1 further comprising a metal contact in direct contact with said narrow bandgap semiconductor film wherein said metal contact comprises a Ti/Au bi-layer contact.

13. The transistor of claim 1 wherein said silicon layer is a silicon body having a top surface opposite a bottom surface formed on an insulating substrate, and wherein said gate dielectric is formed on said top surface and said sidewalls of said silicon body and said gate electrode is formed on said gate dielectric on the top surface of said silicon body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body.

14. A transistor comprising:

a gate dielectric layer formed on a first surface of a silicon layer;

a gate electrode having a pair of laterally opposite sidewalls formed on said gate dielectric layer;

a pair of sidewall spacers formed adjacent to said pair of laterally opposite sidewalls of said gate electrode;

a pair of source/drain regions formed from an epitaxial narrow bandgap semiconductor film having a work function of less than 0.75 eV and a electron mobility greater than 10,000 cm²V<sup>−

1</sup>s<sup>−

1</sup> wherein said narrow bandgap semiconductor extends beneath said gate dielectric layer and has a top surface extending above said first surface of said silicon layer; and

a pair of non-alloyed contacts in direct contact with said low bandgap semiconductor.

15. The transistor of claim 14 wherein said low bandgap semiconductor is selected group consisting of indium antimonide (Insb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs(x>

50%)) and indium phosphide (InP).

16. The transistor of claim 14 wherein said contact comprises a bi-layer titanium/gold contact.

17. The transistor of claim 14 wherein said low bandgap semiconductor is doped to an n type conductivity with a dopant selected from the group consisting of Te or Si.

18. The transistor of claim 14 wherein said low bandgap semiconductor is doped to a p type conductivity and wherein said dopant is carbon.

19. The transistor of claim 14 wherein said silicon layer is a portion of a monocrystalline silicon substrate.

20. The transistor of claim 14 wherein said silicon layer is an epitaxial silicon film formed on a buried oxide layer formed on a silicon substrate.

21. A method of forming a transistor comprising:

forming a gate electrode on a gate dielectric layer formed on a silicon layer; and

forming a pair of source/drain regions on opposite sides of said gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film.

22. The method of claim 21 wherein said narrow bandgap semiconductor film is selected from the group consisting of indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (In_1-xGa_xAs(x>

50%)) and indium phosphide (InP).

23. The method of claim 21 wherein said narrow bandgap semiconductor has a energy bandgap of less than 0.75 eV.

24. A method of forming a transistor comprising:

forming a gate dielectric layer on a first surface of a silicon layer;

forming a gate electrode on said gate dielectric layer, said gate electrode having a pair of laterally opposite sidewalls;

forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode;

etching a pair of recesses into said silicon layer adjacent to said outside edges of said sidewall spacers and beneath said gate electrode formed on said gate dielectric layer; and

depositing a narrow bandgap semiconductor film in said recesses.

25. The method of claim 24 wherein said narrow bandgap semiconductor has an energy bandgap of less than 0.75 eV.

26. The method of claim 24 wherein said narrow bandgap semiconductor film is deposited at a temperature less than 550°

C.

27. The method of claim 24 wherein said narrow bandgap semiconductor film is deposited in said recesses until said narrow bandgap semiconductor film extends above said first surface.

28. The method of claim 24 wherein said narrow bandgap semiconductor film is doped to an n type conductivity while depositing said narrow bandgap semiconductor film.

29. The method of claim 24 wherein said low bandgap semiconductor film is doped to a p type conductivity while depositing said low bandgap semiconductor film.

30. The method of claim 24 further comprises a step of forming a non-alloy contact onto said low bandgap semiconductor film.

31. The method of claim 30 further comprising forming a contact comprising titanium/gold in direct contact with said low bandgap semiconductor film.

32. The method of claim 24 wherein said recesses are etched with a wet etchant comprising an ammonium hydroxide or asyemmtric or symmetric tetra (alkyl) ammonium hydroxides (alkyl=methyl, ethyl, propyl, isopropyl, butyl, tert-butyl;

symmetric meaning all 4 alkyl groups are the same.

33. The method of claim 24 wherein said narrow bandgap semiconductor film is a selectively grown epitaxial film.

34. The method of claim 33 wherein said narrow bandgap semiconductor is indium antimonide (InSb) grown by a MOCVD process utilizing an equimolar gaseous mixture of volatized trimethylindium and stibane (SbH₃) with about 5% each by mass in a carrier gas such as argon.