Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals

• US 20060186915A1
• Filed: 03/29/2006
• Published: 08/24/2006
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
• Original Assignee: Carl Werner, Mark Horowitz, Pak Chau, Scott Best, Stefanos Sidiropoulos
• Inventors: Sidiropoulos, Stefanos, Horowitz, Mark, Best, Scott, Chau, Pak, Werner, Carl
• Granted Patent: US 7,456,778 B2
• Time in Patent Office: Days
• US Class Current: 326/21
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Claims

1. A multiple pulse amplitude modulated driver (multi-PAM driver), comprising:

a data signal terminal; and

first and second driver circuits coupled with the data signal terminal to drive alternating data symbols communicated by the multi-PAM driver via the data signal terminal, wherein the first and second driver circuits include a first plurality of binary weighted driver transistors.

2. The multi-PAM driver of claim 1, wherein the first driver circuit is to drive an even data symbol communicated by the multi-PAM driver via the data signal terminal and the second driver circuit is to drive an odd data symbol via the data signal terminal.

3. The multi-PAM driver of claim 1, further comprising a clock input terminal to receive a clock signal, wherein the multi-PAM driver is to communicate an odd data symbol via the data signal terminal on a first edge of the clock signal and the multi-PAM driver is to communicate an even data symbol via the data signal terminal on a second edge of the clock signal.

4. The multi-PAM driver of claim 1, wherein the first drive circuit includes a first subset of the first plurality of binary weighted driver transistors and the second drive circuit includes a second subset of the first plurality of binary weighted driver transistors, the multi-PAM driver further comprising a multiplexer to selectively couple signals associated with odd and even data symbols from respective ones of the first and second driver circuits onto the data signal terminal based on a clock signal.

5. The multi-PAM driver of claim 1, wherein a respective data symbol includes a least significant bit and a most significant bit, the multi-PAM driver further comprising:

a first encoder in the first driver circuit to receive first input data corresponding to even data symbols and to output encoded signals corresponding to the even data symbols; and

a second encoder in the second driver circuit to receive second input data corresponding to odd data symbols and to output encoded signals corresponding to the odd data symbols.

6. The multi-PAM driver of claim 1, wherein a respective driver circuit includes a plurality of differential pairs of transistors each coupled to a corresponding voltage controlled current source, and wherein a first transistor in a respective differential pair of transistors is coupled to a first input terminal to receive a signal corresponding to a respective data symbol and a second transistor in the respective differential pair of transistors is coupled to a second input terminal to receive a reference signal.

7. The multi-PAM driver of claim 6, wherein the corresponding voltage controlled current source is to adjust a voltage drop over the respective differential pair.

8. The multi-PAM driver of claim 1, further comprising a plurality of equal sized transistors coupled in parallel with respective ones of at least a subset of the first plurality of binary weighted driver transistors.

9. The multi-PAM driver of claim 1, further comprising a second plurality of transistors, wherein a respective one of the second plurality of transistors and a respective one of the first plurality of binary weighted driver transistors are coupled in series as a respective pair of transistors, and wherein a respective pair of transistors are in parallel with other pairs of transistors in a respective drive circuit.

10. The multi-PAM driver of claim 9, wherein the one of the second plurality of transistors in the respective pair of transistors is coupled to a corresponding current control bit signal terminal to receive a respective current control bit signal, and wherein the one of the first plurality of binary weighted driver transistor in the respective pair of transistors is coupled to an input terminal to receive a signal corresponding to a respective data symbol.

11. The multi-PAM driver of claim 1, wherein the first and second driver circuits share the first plurality of binary weighted driver transistors, the multi-PAM driver further comprising a switching circuit to selectively couple signals associated with the odd and even data symbols onto gates of the first plurality of binary-weighted driver transistors.

12. The multi-PAM driver of claim 11, wherein the switching circuit includes at least one multiplexer having at least one pair of pass-gate devices.

13. The multi-PAM driver of claim 1, further comprising:

a plurality of current control bit signal terminals to receive a plurality of current control bit signals; and

a plurality of current control transistors,

wherein a respective current control bit signal terminal in the plurality of current control bit signal terminals is coupled to a respective current control transistor in the plurality of current control transistor, and wherein the respective current control transistor is coupled to a corresponding binary weighted drive transistor.

14. The multi-PAM driver of claim 13, wherein the respective current-control transistor is paired with the corresponding binary weighted transistor, and wherein the respective current-control transistor is positioned between the corresponding binary weighted transistor and the data signal terminal.

15. The multi-PAM driver of claim 13, wherein the respective current-control transistor is paired with the corresponding binary weighted transistor, and wherein the corresponding binary weighted transistor is positioned between the respective current-control transistor and the data signal terminal.

16. The multi-PAM driver of claim 1, further comprising a current control circuit comprising:

a source calibration signal circuit to supply at least one source calibration signal;

a voltage generator to provide a reference voltage signal; and

a comparator coupled to the voltage generator and the source calibration signal circuit; and

a source calibration signal adjustment circuit to adjust the at least one source calibration signal in accordance with an output signal of the comparator.

17. The multi-PAM driver of claim 16, wherein adjustment of the at least one source calibration signal includes adjustment of current output by at least a respective binary weighted driver transistor.

18. The multi-PAM driver of claim 16, wherein the source calibration signal is coupled to the comparator via a coupling network.

19. The multi-PAM driver of claim 18, wherein the coupling network selectively couples the at least one source calibration signal to the comparator.

20. A multiple pulse amplitude modulated driver (multi-PAM driver), comprising:

a first encoder to receive input data associated with even data symbols and to output encoded signals associated with the even data symbols;

a second encoder to receive input data associated with odd data symbols and to output encoded signals associated with the odd data symbols;

a data signal terminal;

a driver circuit coupled with the data signal terminal, the driver circuit including a plurality of binary weighted driver transistors; and

a switching circuit for selectively coupling odd and even data symbols that are to be driven by the drive circuit to the data signal terminal.