Translator circuit and method therefor

• US 20060186922A1
• Filed: 02/18/2005
• Published: 08/24/2006
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Rozsypal, Antonin
• Granted Patent: US 7,176,723 B2
• Time in Patent Office: Days
• US Class Current: 326/63
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit

Abstract

In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.

Claims

1. A method of forming a translator comprising:

configuring the translator to receive an input signal and shift a voltage value of the input signal to form an output signal operably coupled to control a power transistor coupled to an inductive load; and

configuring the translator to receive a supply voltage and inhibit the output signal from changing state responsively to a change in a value of the supply voltage.

2. The method of claim 1 wherein configuring the translator to receive the supply voltage and inhibit the output signal from changing state responsively to the change in the value of the supply voltage includes configuring the translator to receive the supply voltage and inhibit the output signal responsively to a dv/dt produced by the inductive load.

3. The method of claim 2 wherein configuring the translator to receive the supply voltage and inhibit the output signal responsively to the dv/dt produced by the inductive load includes inhibiting the output signal responsively to the dv/dt of no less than approximately ten V/nsec.

4. The method of claim 1 wherein configuring the translator to receive the supply voltage and inhibit the output signal from changing state responsively to the change in the value of the supply voltage includes configuring the translator to clamp the output signal responsively to a voltage that is substantially equal to the value of the supply voltage.

5. The method of claim 1 wherein configuring the translator to receive the supply voltage and inhibit the output signal responsively to the change in the value of the supply voltage includes configuring the translator to sense the supply voltage and inhibit the output signal from changing state responsively to the supply voltage changing at least approximately ten V/nsec.

6. The method of claim 1 wherein configuring the translator to receive the supply voltage and disable the output signal responsively to the change in the value of the supply voltage includes coupling a capacitor to sense the change in the supply voltage and responsively form a sense signal.

7. The method of claim 6 further including coupling the capacitor to form a current flow through a series connected resistor responsively to sensing the change in the supply voltage and responsively form the sense signal.

8. The method of claim 6 further including coupling a transistor to receive the sense signal and responsively clamp the output signal to a voltage that is substantially equal to the supply voltage.

9. The method of claim 1 wherein configuring the translator to receive the supply voltage and disable the output signal responsively to the change in the value of the supply voltage includes coupling a transistor to disable the translator from changing state responsively to the change in the supply voltage.

10. A translator comprising:

a first transistor coupled to receive an input signal having a first maximum voltage value and form an output signal having a second maximum voltage value that is greater than the first maximum voltage value; and

a second transistor coupled to inhibit the translator from changing a state of the output signal responsively to sensing a first change in a value of an input voltage received by the translator.

11. The translator of claim 10 further including a first capacitor coupled to receive the first change in the value of the input voltage and responsively enable the second transistor.

12. The translator of claim 11 further including a first resistor coupled to receive a charging current of the first capacitor and form a voltage to enable the second transistor.

13. The translator of claim 12 wherein a first terminal of the first capacitor is coupled to a supply return, a second terminal is commonly coupled to a control electrode of the second transistor and a first terminal of the first resistor, a second terminal of the first resistor is coupled to receive the input voltage and to a first current carrying electrode of the second transistor, a second current carrying electrode of the second transistor is coupled to a first current carrying electrode of the first transistor, and a second current carrying electrode of the first transistor is coupled to the supply return.

14. The translator of claim 13 further including a second resistor having a first terminal coupled to receive the input voltage and a second terminal coupled to the first current carrying electrode of the second transistor.

15. A method for shifting a voltage level of a signal comprising:

receiving an input signal;

increasing a voltage value of the input signal to form an output signal;

receiving a supply voltage having a first value;

sensing a change in the first value of the supply voltage; and

enabling a clamping circuit to disable the output signal from changing state responsively to detecting the change in the first value of the supply voltage.

16. The method of claim 15 wherein sensing the change in the first value of the supply voltage includes forming a charging current to a first capacitor responsively to the change in the first value of the supply voltage to responsively enable the clamping circuit.

17. The method of claim 16 further including directing the charging current through a resistor in series between the first capacitor and the supply voltage.

18. The method of claim 15 wherein sensing the change in the first value of the supply voltage includes sensing the change that is no less than about ten V/nsec.