Interface circuit

• US 20060186923A1
• Filed: 02/07/2006
• Published: 08/24/2006
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Compound Semiconductor Devices, Ltd. (NEC Corporation)
• Inventors: Wang, Jianqin
• Granted Patent: US 7,327,164 B2
• Time in Patent Office: Days
• US Class Current: 326/75
• CPC Class Codes: H03K 19/001 in bipolar transistor circuits
• CPC Class Codes: H03K 19/01812 with at least one differential stage

Abstract

An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.

Claims

1. An interface circuit comprising:

a first and a second input terminal;

a first output transistor;

a second output transistor;

a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state; and

a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.

2. The interface circuit according to claim 1, comprising:

a first transistor connected to the first input terminal, for outputting a current according to a voltage at the first input terminal;

a first voltage generator for outputting a voltage according to an output of the first transistor;

a second transistor connected to the second input terminal, for outputting a current according to a voltage at the second input terminal; and

a second voltage generator for outputting a voltage according to an output of the second transistor.

3. The interface circuit according to claim 2, wherein the first output controller implements control according to outputs of the first and the second voltage generator so that a predetermined current appears at a control terminal of the first output transistor if the first transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first transistor is in shutoff state.

4. The interface circuit according to claim 2, wherein the second output controller implements control according to outputs of the first and the second voltage generator so that a predetermined current appears at a control terminal of the second output transistor if the second transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second transistor is in shutoff state.

5. The interface circuit according to claim 2, wherein the first voltage generator comprises a third transistor for generating a voltage according to a current generated according to an input of the first transistor.

6. The interface circuit according to claim 2, wherein the second voltage generator comprises a fourth transistor for generating a voltage according to a current generated according to an input of the second transistor.

7. The interface circuit according to claim 1, wherein the first and the second output transistor are connected serially between a first power supply and a second power supply or a third power supply.

8. The interface circuit according to claim 1, wherein the first output controller comprises a fifth transistor and a sixth transistor that are connected serially between a first power supply and a second power supply.

9. The interface circuit according to claim 8, wherein the first output controller comprises a seventh transistor and a second current source that are connected serially between the first power supply and a third power supply.

10. The interface circuit according to claim 1, wherein the second output controller comprises a seventh transistor and an eighth transistor that are connected serially between a first power supply and a second power supply.

11. The interface circuit according to claim 1, wherein the first output controller implements control so that a predetermined current appears at a control terminal of the first output transistor if the first transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first transistor is in shutoff state according to outputs of a first transistor connected to the first input terminal and outputting a current according to a voltage at the first input terminal and a first voltage generator for outputting a voltage according to an output of the first transistor, and a second transistor connected to the second input terminal and outputting a current according to a voltage at the second input terminal and a second voltage generator for outputting a voltage according to an output of the second transistor.

12. The interface circuit according to claim 1, wherein the second output controller implements control so that a predetermined current appears at a control terminal of the second output transistor if the second transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second transistor is in shutoff state according to outputs of a first transistor connected to the first input terminal and outputting a current according to a voltage at the first input terminal and a first voltage generator for outputting a voltage according to an output of the first transistor, and a second transistor connected to the second input terminal and outputting a current according to a voltage at the second input terminal and a second voltage generator for outputting a voltage according to an output of the second transistor.