Temperature-compensated ferroelectric capacitor device, and its fabrication

• US 20060189003A1
• Filed: 08/19/2005
• Published: 08/24/2006
• Est. Priority Date: 09/26/2002
• Status: Active Grant

• Current Assignee: Dougherty T. Kirk, John J. Drab
• Original Assignee: Dougherty T. Kirk, John J. Drab
• Inventors: Drab, John J., Dougherty, T. Kirk
• Granted Patent: US 8,053,251 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A temperature-compensated capacitor device has ferroelectric properties and includes a ferroelectric capacitor using a ferroelectric material such as a metal oxide ferroelectric material, a negative-temperature-variable capacitor using a negative-temperature-coefficient-of-capacitance material such as a metal oxide paraelectric material, and an electrical series connection between the negative-temperature-variable capacitor and the ferroelectric capacitor. The temperature-compensated capacitor device may be formed as an integrated layered structure, or as separate capacitors with a discrete electrical connection therebetween.

Claims

1-16. -16. (canceled)

17. A method for fabricating and using a memory device including a temperature-compensated capacitor having ferroelectric properties, comprising the steps of:

fabricating a temperature-compensated capacitor device including

a ferroelectric capacitor comprising a ferroelectric material,

a negative-temperature-variable capacitor comprising a negative-temperature-coefficient-of-capacitance material, and

an electrical series connection between the negative-temperature-variable capacitor and the ferroelectric capacitor;

incorporating the temperature-compensated capacitor device into a memory device; and

utilizing the memory device to store and retrieve information over an operating temperature range.

18. The method of claim 17, wherein the step of fabricating includes the step of

forming the electrical series connection comprising a direct physical contact between the ferroelectric capacitor and the negative-temperature-variable capacitor.

19. The method of claim 17, wherein the step of fabricating includes the step of

forming the electrical series connection comprising a discrete electrical connection extending between the ferroelectric capacitor and the negative-temperature-variable capacitor.

20. The method of claim 17, wherein the step of fabricating includes the step of

forming the negative-temperature-coefficient-of-capacitance material in direct, facing contact with the ferroelectric layer.

21. The method of claim 17, wherein the step of fabricating includes the step of

selecting the ferroelectric material as a metal oxide ferroelectric material.

22. The method of claim 17, wherein the step of fabricating includes the step of

selecting the ferroelectric material as a metal oxide ferroelectric material selected from the group consisting of lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium titanate, strontium bismuth tantalate, strontium bismuth niobate, strontium bismuth tantalate niobate, and bismuth lead titanate.

23. The method of claim 17, wherein the step of fabricating includes the step of

selecting the negative-temperature-coefficient-of-capacitance material as a paraelectric material.

24. The method of claim 17, wherein the step of fabricating includes the step of

selecting the negative-temperature-coefficient-of-capacitance material as a metal oxide negative-temperature-coefficient-of-capacitance material.

25. The method of claim 17, wherein the step of fabricating includes the step of

selecting the negative-temperature-coefficient-of-capacitance material as a metal oxide negative-temperature coefficient-of-capacitance material selected from the group consisting of strontium titanate and barium strontium titanate.

26. The method of claim 17, wherein the step of fabricating includes the step of

selecting be negative-temperature-coefficient-of-capacitance material as barium strontium titanate.

27. The method of claim 17, wherein the step of utilizing includes the step of

utilizing the memory device over an operating temperature range of from 25°

C. to 125°

C.

28. A method for fabricating and using a memory device including a temperature-compensated capacitor having ferroelectric properties, comprising the steps of:

fabricating a temperature-compensated capacitor device including

a ferroelectric capacitor comprising a ferroelectric material, wherein the ferroelectric material is a metal oxide ferroelectric material selected from the group consisting of lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium titanate, strontium bismuth tantalate, strontium bismuth niobate, strontium bismuth tantalate niobate, and bismuth lead titanate,

a negative-temperature-variable capacitor comprising barium strontium titanate negative-temperature-coefficient-of-capacitance material, and

an electrical series connection between the negative-temperature-variable capacitor and the ferroelectric capacitor;

incorporating the temperature-compensated capacitor device into a memory device; and

utilizing the memory device to store and retrieve information over an operating temperature range.

29. The method of claim 28, wherein the step of fabricating includes the step of

forming the electrical series connection comprising a direct physical contact between the ferroelectric capacitor and the negative-temperature-variable capacitor.

30. The method of claim 28, wherein the step of fabricating includes the step of

forming the electrical series connection comprising a discrete electrical connection extending between the ferroelectric capacitor and the negative-temperature-variable capacitor.

31. The method of claim 28, wherein the step of utilizing includes the step of

utilizing the memory device over an operating temperature range of from 25°

C. to 125°

C.

32. A method for fabricating and using a memory device including a temperature-compensated capacitor having ferroelectric properties, comprising the steps of:

fabricating the temperature-compensated capacitor by

providing a first electrode layer,

depositing a ferroelectric precursor layer of a ferroelectric precursor material on the first electrode layer,

reacting the ferroelectric precursor layer to produce a ferroelectric layer,

depositing a negative-temperature-variable precursor layer of a negative-temperature-coefficient-of-capacitance material on the ferroelectric layer,

reacting the negative-temperature-variable precursor layer to form a paraelectric layer,

placing a second electrode layer on the paraelectric layer, and

operably electrically connecting a memory readout circuit to the ferroelectric capacitor and to the negative-temperature-variable capacitor; and

utilizing the temperature-compensated capacitor in a memory device to store and retrieve information over an operating temperature range.

33. The method of claim 32, wherein the step of providing the first electrode layer includes the step of

depositing the first electrode layer, and wherein the step of placing a second electrode layer includes the step of

depositing the second electrode layer.

34. The method of claim 32, wherein the step of depositing the ferroelectric precursor layer includes the step of

depositing a precursor of a metal oxide ferroelectric material.

35. The method of claim 32, wherein the step of depositing the temperature-variable precursor layer includes the step of

depositing a precursor of a metal oxide negative-negative-temperature-coefficient-of-capacitance material.

36. The method of claim 32, wherein the step of utilizing includes the step of

utilizing the memory device over an operating temperature range of from 25°

C. to 125°

C.