Semiconductor device and control method

• US 20060189011A1
• Filed: 04/24/2006
• Published: 08/24/2006
• Est. Priority Date: 11/19/2002
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Manabu, Kohara, Masaru, Oishi, Shohei, Kawamichi, Koji
• Application Number:
  US11/409,208
• Publication Number:
  US 20060189011A1
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches

Abstract

In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first dead time at a rise of a first PWM signal. On the other hand, time elapsing until the value of the timer reaches a set value of another register is added as a second dead time at a rise of a second PWM signal.

Claims

1-11. -11. (canceled)

12. A method for controlling an apparatus including an inverter circuit with a coil comprising the steps of:

generating a first PWM signal and a second PWM signal corresponding to an inverted signal of the fast PWM signal;

calculating a first dead time and a second dead time, the first dead time determined in response to a comparison between a count value of a timer and a first value stored in a register and the second dead time determined in response to a comparison between a count value of a timer and a second value stored in a register;

delaying a first edge of the first PWM signal by a first delay value corresponding to the first dead time and a second edge of the second PWM signal by a second delay value corresponding to the second dead time, the second edge of the second PWM signal having the same direction of change as that of the first edge of the first PWM signal; and

supplying a modified first PWM signal having the first delayed edge instead of the first edge and a modified second PWM signal having the delayed second edge instead of the second edge to the inverter circuit.

13. The method of claim 12 further comprising the steps of:

detecting a signal output from the inverter circuit; and

updating, upon the detection of the signal, either the first value stored in a register or the second value stored in a register.

14. The method of claim 13, wherein the signal output from the inverter circuit indicates a result of detection of excess current or excess voltage in the apparatus.

15. The method of claim 13 further comprising the steps of:

converting the signal output from the inverter circuit to digital data;

comparing the digital data with a given range which shows a normal operation of the apparatus; and

determining, in response to the comparison, whether either the first value or the second value is updated or not.