Strained channel complementary field-effect transistors and methods of manufacture

• US 20060189056A1
• Filed: 04/20/2006
• Published: 08/24/2006
• Est. Priority Date: 08/12/2003
• Status: Active Grant

• Current Assignee: Chenming Hu, Chih Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo
• Original Assignee: Chenming Hu, Chih Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo
• Inventors: Yeo, Yee-Chia, Lee, Wen-Chin, Ko, Chih-Hsin, Hu, Chenming
• Granted Patent: US 7,442,967 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Claims

1. A transistor comprising:

a gate dielectric overlying a channel region;

a source region and a drain region on opposing sides of the channel region, the channel region comprising a first semiconductor material and the source and drain regions comprising a second semiconductor material;

a gate electrode overlying the gate dielectric; and

first and second spacers formed on sides of the gate electrode, each of the spacers including a void adjacent the channel region.

2. The transistor of claim 1 and further comprising a high-stress film overlying the gate electrode and spacers.

3. The transistor of claim 1 wherein the high-stress film comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide, and combinations thereof.

4. The transistor of claim 1 wherein each spacer includes a liner oxide and a spacer body.

5. The transistor of claim 4 wherein the void is disposed in the liner oxide of the spacer.

6. The transistor of claim 1 wherein the liner oxide comprises silicon oxide and the spacer body comprises silicon nitride.

7. The transistor of claim 1 wherein the transistor is a p-channel transistor.

8. A semiconductor chip comprising:

a semiconductor substrate;

a first transistor formed in the semiconductor substrate, the first transistor having a first channel region formed from a first semiconductor material and having a first source and a first drain region formed in the substrate oppositely adjacent the first channel region, the first source and the first drain region comprising a second semiconductor material that is lattice-mismatched with the first semiconductor material; and

a second transistor formed in the semiconductor substrate and having a conductivity type different than a conductivity type of the first transistor, the second transistor having a second channel region formed from the first semiconductor material, the second transistor also having a second source and a second drain region formed in the substrate oppositely adjacent the second channel region, the second source and second drain regions comprising a material different than the second semiconductor material.

9. The semiconductor chip of claim 8 and further comprising a high-stress film overlying both the first transistor and the second transistor.

10. The semiconductor chip of claim 8 wherein the first transistor further comprises a first spacer adjacent a first gate electrode that overlies the first channel region, the first spacer including a first void formed therein, and wherein the second transistor further comprises a second spacer adjacent a second gate electrode that overlies the second channel region, the second spacer including a second void formed therein.

11. The semiconductor chip of claim 10 wherein the first spacer and the second spacer each have a dielectric liner, and wherein the first void and the second void are located in the dielectric liner.

12. The semiconductor chip of claim 10 wherein the first void has a length in the range of about 20 to about 200 angstroms.

13. The semiconductor chip of claim 12 wherein the second void has a length less than about 100 angstroms.

14. The semiconductor chip of claim 10 wherein the first void and the second void have different sizes.

15. The semiconductor chip of claim 14 wherein the first void is larger than the second void.

16. The semiconductor chip of claim 8 wherein the first semiconductor material has a first natural lattice constant, and the second semiconductor material has a second natural lattice constant, and wherein the second natural lattice constant is larger than the first natural lattice constant.

17. The semiconductor chip of claim 16 wherein at least a portion of the first channel region is under compressive strain in the source-to-drain direction.

18. A semiconductor device comprising:

a silicon substrate;

a p-channel transistor formed within and above the silicon substrate, the p-channel transistor comprising;

a first channel region located within the silicon substrate;

a first source region and a first drain region formed in the substrate oppositely adjacent the first channel region, the first source region and the first drain region being formed from a second semiconductor material that has a natural lattice constant that is different than a natural lattice constant of silicon;

a first gate electrode insulatively overlying the first channel region;

a first spacer region formed adjacent a sidewall of the first gate, the first spacer region including a void adjacent the first channel;

an n-channel transistor formed within and above the silicon substrate, the second transistor comprising;

a second channel region formed within the silicon substrate;

a second source region and a second drain region formed in the substrate oppositely adjacent the second channel region, the second source and second drain regions being formed from a material different than the second semiconductor material;

a high-stress film overlying at least one of the first transistor and the second transistor.

19. The device of claim 18 wherein the second source region and the second drain region are formed within the silicon substrate.

20. The device of claim 18 wherein the second source region and the second drain region are formed from a third semiconductor material that has a natural lattice constant that is different than the natural lattice constant of silicon and the natural lattice constant of the second semiconductor material.