Semiconductor device and method of manufacturing the same

• US 20060189070A1
• Filed: 04/29/2005
• Published: 08/24/2006
• Est. Priority Date: 02/21/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yasutake, Hitomi, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru
• Granted Patent: US 7,145,197 B2
• Time in Patent Office: Days
• US Class Current: 438/243
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor

Abstract

A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first to third side surfaces in the upper portion of the element region, a gate electrode having first and second bottom surfaces, a first diffusion layer formed along the upper surface of the element region, a second diffusion layer formed along the first side surface in the middle portion of the element region, a channel region having first to third regions formed along the first to third side surfaces in the upper portion of the element region, a capacitor formed in the trench, and a bit line electrically connected to the first diffusion layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a trench formed in the semiconductor substrate;

an island-like element region formed in the semiconductor substrate, having an upper surface, a first side surface exposed by the trench, a second side surface, and a third side surface opposing the second side surface, and having an upper portion including the upper surface, a middle portion positioned below the upper portion, and a lower portion positioned below the middle portion;

a gate insulating film formed on the first to third side surfaces in the upper portion of the element region;

a gate electrode having a portion extending over the upper surface of the element region and the second and third side surfaces in the upper portion of the element region, and having a first bottom surface positioned above the upper surface of the element region, and a second bottom surface positioned below the upper surface of the element region;

a first diffusion layer formed along the upper surface of the element region;

a second diffusion layer formed along the first side surface in the middle portion of the element region;

a channel region having a first region formed along the first side surface in the upper portion of the element region, a second region formed along the second side surface in the upper portion of the element region, and a third region formed along the third side surface in the upper portion of the element region;

a capacitor formed in the trench and adjacent to the lower portion of the element region; and

a bit line electrically connected to the first diffusion layer.

2. The device according to claim 1, further comprising an element isolation insulating film having an upper surface positioned below the upper surface of the element region.

3. The device according to claim 2, wherein a height of the upper surface of the element isolation insulating film is equal to a height of the second bottom surface of the gate electrode.

4. The device according to claim 1, further comprising a groove formed in an upper portion of the trench, having a depth shallower than a depth of the trench, and having an opening larger than an opening of the trench.

5. The device according to claim 4, wherein a bottom surface of the groove is in contact with the second bottom surface of the gate electrode.

6. The device according to claim 1, further comprising:

a groove formed in an upper portion of the trench, having a depth shallower than a depth of the trench, and having an opening larger than an opening of the trench; and

an element isolating insulating film formed below the groove.

7. The device according to claim 6, wherein heights of a bottom surface of the groove and an upper surface of the element isolation insulating film are equal to a height of the second bottom surface of the gate electrode.

8. The device according to claim 6, wherein a bottom surface of the groove is in contact with the second bottom surface of the gate electrode.

9. The device according to claim 1, further comprising:

a connecting portion formed in the trench and connected to the capacitor; and

an interface layer formed on an inner side surface of the trench between the second diffusion layer and connecting portion.

10. The device according to claim 1, further comprising a pad formed between the upper surface of the element region and the first bottom surface of the gate electrode.

11. The device according to claim 1, wherein the capacitor comprises:

a lower electrode formed along an outer side surface and outer bottom surface of the trench, and made of a diffusion layer;

a capacitor insulating film formed on an inner side surface and inner bottom surface of the trench; and

an upper electrode formed on the capacitor insulating film in the trench, and electrically connected to the second diffusion layer.

12. The device according to claim 1, wherein the first diffusion layer comprises:

a low-concentration region; and

a high-concentration region formed contiguously with the low-concentration region.

13. The device according to claim 1, further comprising a silicide layer formed on the gate electrode.

14. A method of manufacturing a semiconductor device, comprising:

forming a trench having an upper portion, middle portion, and lower portion in a semiconductor substrate;

forming a capacitor in the lower portion of the trench;

forming, in the middle portion of the trench, a connecting portion which connects to the capacitor;

forming an insulating film in the upper portion of the trench;

selectively removing the insulating film to form a groove;

forming a gate insulating film on a side surface of the groove;

forming a gate electrode having a first bottom surface positioned above an upper surface of the semiconductor substrate, and a second bottom surface positioned below the upper surface of the semiconductor substrate;

forming a first diffusion layer on the upper surface of the semiconductor substrate, and a second diffusion layer along an outer side surface of the middle portion of the trench; and

forming a bit line which electrically connects to the first diffusion layer.

15. The method according to claim 14, in which the semiconductor substrate comprises an island-like element region having an upper surface, a first side surface exposed by the upper portion of the trench, a second side surface, and a third side surface opposing the second side surface, and

which further comprises forming a channel region having a first region formed along the first side surface of the element region, a second region formed along the second side surface of the element region, and a third region formed along the third side surface of the element region.

16. The method according to claim 15, wherein the gate insulating film is formed on the first to third side surfaces of the element region.

17. The method according to claim 14, wherein the second bottom surface of the gate electrode is in contact with a bottom surface of the groove.

18. The method according to claim 14, further comprising forming an element isolation insulating film positioned below the groove.

19. The method according to claim 14, further comprising forming an interface layer between the second diffusion layer and connecting portion.

20. The method according to claim 14, further comprising forming a pad between the upper surface of the semiconductor substrate and the first bottom surface of the gate electrode.