Method for making high-density nonvolatile memory

• US 20060189077A1
• Filed: 04/10/2006
• Published: 08/24/2006
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mahajani, Maitreyee, Herner, S. Brad
• Granted Patent: US 7,557,405 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Claims

1. A nonvolatile memory cell comprising:

a first conductor at a first height above a substrate and extending in a first direction;

a first polycrystalline semiconductor element above the first conductor, wherein the semiconductor element comprises a heavily doped P-type region and a heavily doped N-type region, and wherein no antifuse layer intervenes between the heavily doped P-type region and the heavily doped N-type region; and

a second conductor above the semiconductor element and extending in a second direction, the second direction substantially different from the first direction,

wherein a portion of the first conductor, the semiconductor element, and a portion of the second conductor make up the nonvolatile memory cell.

2. The nonvolatile memory cell of claim 1 further comprising an antifuse layer disposed between the first semiconductor element and the second conductor.

3. The nonvolatile memory cell of claim 2 wherein the antifuse layer is an oxide layer.

4. The nonvolatile memory cell of claim 3 wherein the oxide layer comprises silicon dioxide.

5. The nonvolatile memory cell of claim 1 wherein the semiconductor element is a vertically oriented pillar.

6. The nonvolatile memory cell of claim 1 wherein the heavily doped P-type region is above the heavily doped N-type region.

7. The nonvolatile memory cell of claim 1 wherein the heavily doped N-type region is above the heavily doped P-type region.

8. The nonvolatile memory cell of claim 1 wherein a lightly doped region is disposed between the heavily doped N-type region and the heavily doped P-type region.

9. The nonvolatile memory cell of claim 1 wherein the substrate comprises monocrystalline silicon.

10. The nonvolatile memory cell of claim 1 wherein the first conductor or the second conductor comprises tungsten.

11. The nonvolatile memory cell of claim 1 wherein the second direction is substantially perpendicular to the first direction.

12. A method to form a nonvolatile memory cell, the method comprising:

i) forming a first conductor at a first height above a substrate;

ii) forming a first pillar-shaped semiconductor element above the first conductor, wherein the first semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first layer, and a third heavily doped layer of a second conductivity type above and in contact with the second layer, the second conductivity type opposite the first;

iii) forming a first antifuse above the third heavily doped layer of the first semiconductor element; and

iv) forming a second conductor above the first dielectric antifuse.

13. The method of claim 12 wherein the step of forming the first semiconductor element comprises:

after the step of forming the first conductor, depositing a semiconductor layer stack on the first conductor; and

patterning and etching the layer stack to form the first semiconductor element.

14. The method of claim 13 wherein the semiconductor layer stack comprises depositing polycrystalline silicon.

15. The method of claim 12 wherein the substrate comprises monocrystalline silicon.

16. The method of claim 12 wherein the first conductivity type is N-type and the second conductivity type is P-type.

17. The method of claim 12 wherein the first conductivity type is P-type and the second conductivity type is N-type.

18. The method of claim 12 wherein the third heavily doped layer is doped by ion implantation.

19. The method of claim 12 wherein the first heavily doped layer is doped by in situ doping.

20. The method of claim 12 wherein the step of forming the first conductor comprises:

depositing a first tungsten layer; and

patterning and etching the first tungsten layer to form the first conductor.

21. The method of claim 12 wherein the first antifuse comprises an oxide layer.

22. The method of claim 21 wherein the oxide layer comprises silicon dioxide.

23. A monolithic three dimensional memory array comprising:

a plurality of substantially parallel first conductors above a substrate, the first conductors not comprising monocrystalline silicon;

a plurality of first semiconductor elements above the first conductors, each semiconductor element comprising a first heavily doped layer of a first conductivity type, a second lightly doped layer, and a third heavily doped layer of a second conductivity type;

a plurality of first antifuse layers, each antifuse layer formed above one of the semiconductor elements; and

a plurality of substantially parallel second conductors, the second conductors above the first antifuse layers.

24. The monolithic three dimensional memory array of claim 23 wherein the substrate comprises monocrystalline silicon.

25. The monolithic three dimensional memory array of claim 23 wherein the first conductors or the second conductors comprise tungsten.

26. The monolithic three dimensional memory array of claim 23 wherein the first semiconductor elements are vertically oriented pillars.

27. The monolithic three dimensional memory array of claim 23 wherein the first semiconductor elements comprise polycrystalline silicon.

28. The monolithic three dimensional memory array of claim 23 wherein the first antifuse layers comprise an oxide.

29. The monolithic three dimensional memory array of claim 28 wherein the oxide comprises silicon oxide.

30. The monolithic three dimensional memory array of claim 23 further comprising a plurality of second semiconductor elements above the second conductors.

31. The monolithic three dimensional memory array of claim 30 further comprising a plurality of third conductors formed above the second semiconductor elements.

32. The monolithic three dimensional memory array of claim 23 further comprising a plurality of memory cells, each memory cell comprising a portion of one of the first conductors, one of the first semiconductor elements, and a portion of one of the second conductors.

33. The monolithic three dimensional memory array of claim 23 wherein the first conductors extend in a first direction, and the second conductors extend in a second direction, the second direction different from the first direction.

34. The monolithic three dimensional memory array of claim 33 wherein the second direction is substantially perpendicular to the first direction.

35. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate;

forming a first plurality of semiconductor elements above the first conductors, each first semiconductor element comprising a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first layer, and a third heavily doped layer on and in contact with the second layer, the third heavily doped layer having a second conductivity type opposite the first conductivity type; and

forming a second plurality of substantially parallel, substantially coplanar conductors above the first semiconductor elements.

36. The method of claim 35 wherein the step of forming the first conductors comprises:

depositing a first conductive layer;

patterning and etching the first conductive layer to form the first conductors;

depositing a first dielectric material over and between the first conductors; and

planarizing to expose tops of the first conductors separated by the first dielectric material.

37. The method of claim 36 wherein the step of forming the first semiconductor elements comprises:

depositing a first semiconductor layer stack on the planarized first dielectric material and first conductors;

patterning and etching the first semiconductor layer stack to form the first semiconductor elements;

depositing a second dielectric material on and between the semiconductor elements; and

planarizing to expose tops of the first semiconductor elements.

38. The method of claim 37 wherein the step of depositing a first semiconductor layer stack comprises depositing polycrystalline silicon.

39. The method of claim 37 wherein the first semiconductor elements are pillar-shaped.

40. The method of claim 35 wherein the third heavily doped layer of each first semiconductor element is doped by ion implantation.

41. The method of claim 35 wherein the first heavily doped layer of each first semiconductor element is doped by in situ doping.

42. The method of claim 35 further comprising forming a second plurality of semiconductor elements above the second conductors.

43. The method of claim 42 further comprising forming a third plurality of substantially parallel, substantially coplanar conductors above the second semiconductor elements.

44. The method of claim 35 further comprising forming a plurality of first antifuse layers disposed between the first semiconductor elements and the second conductors.

45. The method of claim 44 wherein the step of forming the first antifuse layers comprises forming oxide layers.

46. The method of claim 45 wherein the step of forming oxide layers comprises oxidizing a portion of the third heavily doped layer of each semiconductor element.

47. The method of claim 35 wherein the first conductivity type is N-type and the second conductivity type is P-type.

48. The method of claim 35 wherein the first conductivity type is P-type and the second conductivity type is N-type.