METHOD OF MODELING A PORTION OF AN ELECTRICAL CIRCUIT USING A POLE-ZERO APPROXIMATION OF AN S-PARAMETER TRANSFER FUNCTION OF THE CIRCUIT PORTION

• US 20060190229A1
• Filed: 02/23/2005
• Published: 08/24/2006
• Est. Priority Date: 02/23/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mohammad, Amanullah, Pakbaz, Faraydon
• Application Number:
  US10/906,509
• Publication Number:
  US 20060190229A1
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method (1100) of creating a behavioral model of a portion (400) of an electrical circuit. The method includes collecting data by measuring an S-parameter of the circuit portion. A transfer function approximation (412, 1000) is then constructed from the S-parameter data. The transfer function approximation is simplified to provide a partial fraction expansion (416). The behavioral model includes a passive filter (420, 1004) designed to represent the partial fraction expansion.

Claims

1. A method of characterizing a portion of an electrical circuit, comprising:

a) deriving a transfer function for the portion of the electrical circuit based on a measured response of the portion to a known input to the portion; and

b) running a computer simulation as a function of said transfer function.

2. A method according to claim 1, further comprising the step of deriving a partial fraction expansion of said transfer function, step b) including running a computer simulation as a function of said partial fraction expansion.

3. A method according to claim 2, further comprising the step of creating an elemental representation of said partial fraction expansion, step b) including running a computer simulation using said elemental representation.

4. A method according to claim 3, wherein said partial fraction expansion includes a plurality of partial fractions, the step of creating said elemental representation includes representing each of said partial fractions as a circuit segment.

5. A method according to claim 4, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segments as a voltage divider.

6. A method according to claim 4, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segments as a filter.

7. A method according to claim 3, wherein the step of creating an elemental representation of said partial fraction expansion includes representing said elemental representation as a plurality of circuit segments.

8. A method according to claim 7, wherein the step of representing said elemental representation as a plurality of circuit segments includes representing said elemental representation with at least one gain element.

9. A method according to claim 1, wherein the portion of the circuit comprises a communication interconnect and step a) includes deriving a transfer function for the communication interconnect based on a measured response of the communication interconnect to a known input to the communication interconnect.

10. A method of converting S-parameter data to an elemental approximation, comprising:

a) deriving a transfer function from the S-parameter data; and

b) representing said transfer function as an elemental representation.

11. A method according to claim 10, wherein step b) includes the steps of expanding said transfer function into a plurality of partial fractions and representing each of said partial fractions as a circuit segment.

12. A method according to claim 11, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segments as a voltage divider.

13. A method according to claim 11, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segment as a filter.

14. A method according to claim 13, wherein each of said filters has filtering ability, the method further comprising ordering said filters as a function of said filtering ability.

15. A method according to claim 10, wherein step b) includes representing said transfer function as a plurality of circuit elements, wherein at least one of said circuit elements is a gain element.

16. A method of creating a behavioral model of a printed circuit board communication interconnect, comprising:

a) deriving a transfer function for the communication interconnect based on a measured response of the communication interconnect to a known input to the communication interconnect; and

b) running a computer simulation as a function of said transfer function.

17. A method according to claim 16, further comprising the step of deriving a partial fraction expansion of said transfer function, step b) including running a computer simulation as a function of said partial fraction expansion.

18. A method according to claim 17, wherein said partial fraction expansion includes a plurality of partial fractions, the method further including the step of representing each of said partial fractions as a circuit segment.

19. A method according to claim 18, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segments as a voltage divider.

20. A method according to claim 18, wherein the step of representing each of said partial fractions as a circuit segment includes representing each of said circuit segments as a filter.